Design for testability support for launch and capture power reduction in launch-off-shift and launch-off-capture testing

Samah Mohamed Saeed, Ozgur Sinanoglu

Research output: Contribution to journalArticle

Abstract

At-speed or even faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable for lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak-power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose design for testability (DfT) support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner; we develop three different DfT mechanisms, one for launch-off shift, one for launch-off capture, and one for mixed at-speed testing. The proposed DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design-flow-compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering the launch/capture power.

Original languageEnglish (US)
Article number6502264
Pages (from-to)516-521
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number3
DOIs
StatePublished - Mar 2014

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Keywords

  • Design partitioning
  • launch-off capture (LOC)
  • launch-off shift (LOS)
  • peak power reduction
  • test power reduction

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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