Design and implementation of abacus switch: A scalable multicast ATM switch

H. Jonathan Chao, B. S. Choe, J. S. Park, N. Uzun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports and has buffers at input and output ports. A novel algorithm has been proposed to resolve output port contention while and achieves input buffers sharing, fairness among the input ports, and call splitting for multi-casting. The channel grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. A key component for building the Abacus switch called ATM Routing and Contention (ARC) chip has been implemented with CMOS 0.8-μm technology and tested to operate correctly at 240 Mbit/s. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is also presented.

Original languageEnglish (US)
Title of host publicationConference Record / IEEE Global Telecommunications Conference
Editors Anon
PublisherIEEE
Pages854-861
Number of pages8
Volume2
Publication statusPublished - 1996
EventProceedings of the 1996 IEEE Communications Theory Mini-Conference. Part 4 (of 4) - London, UK
Duration: Nov 18 1996Nov 22 1996

Other

OtherProceedings of the 1996 IEEE Communications Theory Mini-Conference. Part 4 (of 4)
CityLondon, UK
Period11/18/9611/22/96

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Global and Planetary Change

Cite this

Chao, H. J., Choe, B. S., Park, J. S., & Uzun, N. (1996). Design and implementation of abacus switch: A scalable multicast ATM switch. In Anon (Ed.), Conference Record / IEEE Global Telecommunications Conference (Vol. 2, pp. 854-861). IEEE.