Design and implementation of abacus switch

A scalable multicast ATM switch

H. Jonathan Chao, Byeong Seog Choe, Jin Soo Park, Necdet Uzun

Research output: Contribution to journalArticle

Abstract

This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32 × 32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz.

Original languageEnglish (US)
Pages (from-to)830-843
Number of pages14
JournalIEEE Journal on Selected Areas in Communications
Volume15
Issue number5
DOIs
StatePublished - Jun 1997

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Automatic teller machines
Switches
Throughput
Multicasting
Application specific integrated circuits
Hardware

Keywords

  • Asynchronous transfer mode
  • Contention resolution
  • Large-scale switches
  • Multicast switches
  • Switching systems

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications

Cite this

Design and implementation of abacus switch : A scalable multicast ATM switch. / Chao, H. Jonathan; Choe, Byeong Seog; Park, Jin Soo; Uzun, Necdet.

In: IEEE Journal on Selected Areas in Communications, Vol. 15, No. 5, 06.1997, p. 830-843.

Research output: Contribution to journalArticle

Chao, H. Jonathan ; Choe, Byeong Seog ; Park, Jin Soo ; Uzun, Necdet. / Design and implementation of abacus switch : A scalable multicast ATM switch. In: IEEE Journal on Selected Areas in Communications. 1997 ; Vol. 15, No. 5. pp. 830-843.
@article{b5291d9bb73e4b72b1126233284d44fb,
title = "Design and implementation of abacus switch: A scalable multicast ATM switch",
abstract = "This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32 × 32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz.",
keywords = "Asynchronous transfer mode, Contention resolution, Large-scale switches, Multicast switches, Switching systems",
author = "Chao, {H. Jonathan} and Choe, {Byeong Seog} and Park, {Jin Soo} and Necdet Uzun",
year = "1997",
month = "6",
doi = "10.1109/49.594845",
language = "English (US)",
volume = "15",
pages = "830--843",
journal = "IEEE Journal on Selected Areas in Communications",
issn = "0733-8716",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - Design and implementation of abacus switch

T2 - A scalable multicast ATM switch

AU - Chao, H. Jonathan

AU - Choe, Byeong Seog

AU - Park, Jin Soo

AU - Uzun, Necdet

PY - 1997/6

Y1 - 1997/6

N2 - This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32 × 32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz.

AB - This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32 × 32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz.

KW - Asynchronous transfer mode

KW - Contention resolution

KW - Large-scale switches

KW - Multicast switches

KW - Switching systems

UR - http://www.scopus.com/inward/record.url?scp=0031170338&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031170338&partnerID=8YFLogxK

U2 - 10.1109/49.594845

DO - 10.1109/49.594845

M3 - Article

VL - 15

SP - 830

EP - 843

JO - IEEE Journal on Selected Areas in Communications

JF - IEEE Journal on Selected Areas in Communications

SN - 0733-8716

IS - 5

ER -