Design and evaluation of a timestamp-based concurrent error detection method (CED) in a modern microprocessor controller

Mihalis Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti

    Research output: Contribution to journalConference article

    Abstract

    This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction executing in the processor. To evaluate the proposed method, we use a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks and we consider the coverage and the detection latency for faults in the scheduler module of the microprocessor controller. Experimental results show that through this method, a large percentage of control logic faults can be detected with low latency during normal operation of the processor.

    Original languageEnglish (US)
    Article number4641203
    Pages (from-to)454-462
    Number of pages9
    JournalProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    DOIs
    StatePublished - Dec 1 2008
    Event23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States
    Duration: Oct 1 2008Oct 3 2008

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    Error detection
    Microprocessor chips
    Controllers

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Design and evaluation of a timestamp-based concurrent error detection method (CED) in a modern microprocessor controller. / Maniatakos, Mihalis; Karimi, Naghmeh; Makris, Yiorgos; Jas, Abhijit; Tirumurti, Chandra.

    In: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 01.12.2008, p. 454-462.

    Research output: Contribution to journalConference article

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