Design and analysis of ring oscillator based Design-for-Trust technique

Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Due to the increasing opportunities for malicious inclusions in hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, hardware overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans in the presence of process variations and measurement errors. This technique can detect Trojans that are inserted in all or a subset of the ICs. It is applicable to both ASICs and FPGA implementations. Circuit paths in a design are reconfigured into ring oscillators1 (ROs) by adding a small amount of logic. Trojans are detected by observing the changes in the frequency of the ROs. An algorithm is provided to secure all the gates, while reducing the hardware overhead. We analyzed the coverage, area and test time overhead of the proposed DFTr technique. To demonstrate its effectiveness in the real world, the proposed technique had been validated by a red-team blue-team approach.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011
Pages105-110
Number of pages6
DOIs
StatePublished - 2011
Event2011 29th IEEE VLSI Test Symposium, VTS 2011 - Dana Point, CA, United States
Duration: May 1 2011May 5 2011

Other

Other2011 29th IEEE VLSI Test Symposium, VTS 2011
CountryUnited States
CityDana Point, CA
Period5/1/115/5/11

Fingerprint

Hardware
Application specific integrated circuits
Measurement errors
Field programmable gate arrays (FPGA)
Networks (circuits)
Costs
Integrated circuit design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Rajendran, J., Jyothi, V., Sinanoglu, O., & Karri, R. (2011). Design and analysis of ring oscillator based Design-for-Trust technique. In Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011 (pp. 105-110). [5783766] https://doi.org/10.1109/VTS.2011.5783766

Design and analysis of ring oscillator based Design-for-Trust technique. / Rajendran, Jeyavijayan; Jyothi, Vinayaka; Sinanoglu, Ozgur; Karri, Ramesh.

Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. p. 105-110 5783766.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rajendran, J, Jyothi, V, Sinanoglu, O & Karri, R 2011, Design and analysis of ring oscillator based Design-for-Trust technique. in Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011., 5783766, pp. 105-110, 2011 29th IEEE VLSI Test Symposium, VTS 2011, Dana Point, CA, United States, 5/1/11. https://doi.org/10.1109/VTS.2011.5783766
Rajendran J, Jyothi V, Sinanoglu O, Karri R. Design and analysis of ring oscillator based Design-for-Trust technique. In Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. p. 105-110. 5783766 https://doi.org/10.1109/VTS.2011.5783766
Rajendran, Jeyavijayan ; Jyothi, Vinayaka ; Sinanoglu, Ozgur ; Karri, Ramesh. / Design and analysis of ring oscillator based Design-for-Trust technique. Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. pp. 105-110
@inproceedings{6a3729a285d54cc68b4fef345bdc7777,
title = "Design and analysis of ring oscillator based Design-for-Trust technique",
abstract = "Due to the increasing opportunities for malicious inclusions in hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, hardware overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans in the presence of process variations and measurement errors. This technique can detect Trojans that are inserted in all or a subset of the ICs. It is applicable to both ASICs and FPGA implementations. Circuit paths in a design are reconfigured into ring oscillators1 (ROs) by adding a small amount of logic. Trojans are detected by observing the changes in the frequency of the ROs. An algorithm is provided to secure all the gates, while reducing the hardware overhead. We analyzed the coverage, area and test time overhead of the proposed DFTr technique. To demonstrate its effectiveness in the real world, the proposed technique had been validated by a red-team blue-team approach.",
author = "Jeyavijayan Rajendran and Vinayaka Jyothi and Ozgur Sinanoglu and Ramesh Karri",
year = "2011",
doi = "10.1109/VTS.2011.5783766",
language = "English (US)",
isbn = "9781612846552",
pages = "105--110",
booktitle = "Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011",

}

TY - GEN

T1 - Design and analysis of ring oscillator based Design-for-Trust technique

AU - Rajendran, Jeyavijayan

AU - Jyothi, Vinayaka

AU - Sinanoglu, Ozgur

AU - Karri, Ramesh

PY - 2011

Y1 - 2011

N2 - Due to the increasing opportunities for malicious inclusions in hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, hardware overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans in the presence of process variations and measurement errors. This technique can detect Trojans that are inserted in all or a subset of the ICs. It is applicable to both ASICs and FPGA implementations. Circuit paths in a design are reconfigured into ring oscillators1 (ROs) by adding a small amount of logic. Trojans are detected by observing the changes in the frequency of the ROs. An algorithm is provided to secure all the gates, while reducing the hardware overhead. We analyzed the coverage, area and test time overhead of the proposed DFTr technique. To demonstrate its effectiveness in the real world, the proposed technique had been validated by a red-team blue-team approach.

AB - Due to the increasing opportunities for malicious inclusions in hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, hardware overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans in the presence of process variations and measurement errors. This technique can detect Trojans that are inserted in all or a subset of the ICs. It is applicable to both ASICs and FPGA implementations. Circuit paths in a design are reconfigured into ring oscillators1 (ROs) by adding a small amount of logic. Trojans are detected by observing the changes in the frequency of the ROs. An algorithm is provided to secure all the gates, while reducing the hardware overhead. We analyzed the coverage, area and test time overhead of the proposed DFTr technique. To demonstrate its effectiveness in the real world, the proposed technique had been validated by a red-team blue-team approach.

UR - http://www.scopus.com/inward/record.url?scp=79959669568&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959669568&partnerID=8YFLogxK

U2 - 10.1109/VTS.2011.5783766

DO - 10.1109/VTS.2011.5783766

M3 - Conference contribution

AN - SCOPUS:79959669568

SN - 9781612846552

SP - 105

EP - 110

BT - Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011

ER -