Design and analysis of enhanced Abacus switch

J. S. Park, H. Jonathan Chao

Research output: Contribution to journalArticle

Abstract

Combined input-output buffering with a moderate speedup for internal switch fabric has been considered as the most feasible solution to build large-capacity packet switches. This paper describes several schemes to further scale up our previously proposed Abacus switch [IEEE J. Select. Areas Commun. 15 (1997) 830] to multiple terabit per second. The Abacus switch implements the arbiter in a distributed manner, allowing the switch to be scaled in both the port speed and the switch capacity. The switch can be easily implemented using crosspoint switch chips with self-routing capability. The enhanced version can also route variable-length packets without doing packet reassembly at the output.

Original languageEnglish (US)
Pages (from-to)577-589
Number of pages13
JournalComputer Communications
Volume25
Issue number6
DOIs
StatePublished - Apr 1 2002

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Keywords

  • Arbitration
  • Input buffered switch
  • Switch architecture
  • Terabit switching

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Design and analysis of enhanced Abacus switch. / Park, J. S.; Chao, H. Jonathan.

In: Computer Communications, Vol. 25, No. 6, 01.04.2002, p. 577-589.

Research output: Contribution to journalArticle

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