Constraint-based placement and routing for FPGAs using self-organizing maps

Mihalis Maniatakos, Songhua Xu, Willard L. Miranker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Field-programmable gate arrays (FPGAs) are becoming increasingly popular due to low design times, easy testing and implementation procedures and low costs. FPGAs placement and routing are NP-complete problems dealt well with modern tools using heuristic algorithms. As modern FPGAs increase in size and also new capabilities, such as Run-Time Reconfiguration (RTR), are introduced, the complexity of these problems is greatly increased. In this paper we approach both problems using a modified version of Kohonen Self-Organizing map. The algorithm, consisting of four phases, takes into consideration constraints that may apply to the FPGA design (such as I/O pins, resource constraints like global clock etc). The modified algorithm yields a good topological map of the design to be placed, minimizing the average distance between connecting logic blocks.

Original languageEnglish (US)
Title of host publicationProceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08
Pages465-469
Number of pages5
Volume2
DOIs
StatePublished - Dec 22 2008
Event20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08 - Dayton, OH, United States
Duration: Nov 3 2008Nov 5 2008

Other

Other20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08
CountryUnited States
CityDayton, OH
Period11/3/0811/5/08

Fingerprint

Self organizing maps
Field programmable gate arrays (FPGA)
Heuristic algorithms
Clocks
Computational complexity
Testing
Costs

Keywords

  • Constraints
  • FPGA
  • Placement
  • Routing
  • Self-organizing feature map

ASJC Scopus subject areas

  • Software
  • Artificial Intelligence
  • Computer Science Applications

Cite this

Maniatakos, M., Xu, S., & Miranker, W. L. (2008). Constraint-based placement and routing for FPGAs using self-organizing maps. In Proceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08 (Vol. 2, pp. 465-469). [4669810] https://doi.org/10.1109/ICTAI.2008.55

Constraint-based placement and routing for FPGAs using self-organizing maps. / Maniatakos, Mihalis; Xu, Songhua; Miranker, Willard L.

Proceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08. Vol. 2 2008. p. 465-469 4669810.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maniatakos, M, Xu, S & Miranker, WL 2008, Constraint-based placement and routing for FPGAs using self-organizing maps. in Proceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08. vol. 2, 4669810, pp. 465-469, 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08, Dayton, OH, United States, 11/3/08. https://doi.org/10.1109/ICTAI.2008.55
Maniatakos M, Xu S, Miranker WL. Constraint-based placement and routing for FPGAs using self-organizing maps. In Proceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08. Vol. 2. 2008. p. 465-469. 4669810 https://doi.org/10.1109/ICTAI.2008.55
Maniatakos, Mihalis ; Xu, Songhua ; Miranker, Willard L. / Constraint-based placement and routing for FPGAs using self-organizing maps. Proceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08. Vol. 2 2008. pp. 465-469
@inproceedings{d3adce82b92c457a9942336ec50d9823,
title = "Constraint-based placement and routing for FPGAs using self-organizing maps",
abstract = "Field-programmable gate arrays (FPGAs) are becoming increasingly popular due to low design times, easy testing and implementation procedures and low costs. FPGAs placement and routing are NP-complete problems dealt well with modern tools using heuristic algorithms. As modern FPGAs increase in size and also new capabilities, such as Run-Time Reconfiguration (RTR), are introduced, the complexity of these problems is greatly increased. In this paper we approach both problems using a modified version of Kohonen Self-Organizing map. The algorithm, consisting of four phases, takes into consideration constraints that may apply to the FPGA design (such as I/O pins, resource constraints like global clock etc). The modified algorithm yields a good topological map of the design to be placed, minimizing the average distance between connecting logic blocks.",
keywords = "Constraints, FPGA, Placement, Routing, Self-organizing feature map",
author = "Mihalis Maniatakos and Songhua Xu and Miranker, {Willard L.}",
year = "2008",
month = "12",
day = "22",
doi = "10.1109/ICTAI.2008.55",
language = "English (US)",
isbn = "9780769534404",
volume = "2",
pages = "465--469",
booktitle = "Proceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08",

}

TY - GEN

T1 - Constraint-based placement and routing for FPGAs using self-organizing maps

AU - Maniatakos, Mihalis

AU - Xu, Songhua

AU - Miranker, Willard L.

PY - 2008/12/22

Y1 - 2008/12/22

N2 - Field-programmable gate arrays (FPGAs) are becoming increasingly popular due to low design times, easy testing and implementation procedures and low costs. FPGAs placement and routing are NP-complete problems dealt well with modern tools using heuristic algorithms. As modern FPGAs increase in size and also new capabilities, such as Run-Time Reconfiguration (RTR), are introduced, the complexity of these problems is greatly increased. In this paper we approach both problems using a modified version of Kohonen Self-Organizing map. The algorithm, consisting of four phases, takes into consideration constraints that may apply to the FPGA design (such as I/O pins, resource constraints like global clock etc). The modified algorithm yields a good topological map of the design to be placed, minimizing the average distance between connecting logic blocks.

AB - Field-programmable gate arrays (FPGAs) are becoming increasingly popular due to low design times, easy testing and implementation procedures and low costs. FPGAs placement and routing are NP-complete problems dealt well with modern tools using heuristic algorithms. As modern FPGAs increase in size and also new capabilities, such as Run-Time Reconfiguration (RTR), are introduced, the complexity of these problems is greatly increased. In this paper we approach both problems using a modified version of Kohonen Self-Organizing map. The algorithm, consisting of four phases, takes into consideration constraints that may apply to the FPGA design (such as I/O pins, resource constraints like global clock etc). The modified algorithm yields a good topological map of the design to be placed, minimizing the average distance between connecting logic blocks.

KW - Constraints

KW - FPGA

KW - Placement

KW - Routing

KW - Self-organizing feature map

UR - http://www.scopus.com/inward/record.url?scp=57649200298&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=57649200298&partnerID=8YFLogxK

U2 - 10.1109/ICTAI.2008.55

DO - 10.1109/ICTAI.2008.55

M3 - Conference contribution

AN - SCOPUS:57649200298

SN - 9780769534404

VL - 2

SP - 465

EP - 469

BT - Proceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08

ER -