Configurable spare processors: A new approach to system level fault-tolerance

Kyosun Kim, Ramesh Karri, Miodrag Potkonjak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A methodology for behavioral synthesis of an important class of reconfigurable data path designs called configurable spare processors is presented. This configurable spare efficiently implements any of k applications and can be configured to substitute for a faulty processor implementing one of these k applications. Three important techniques targeting configurable spare processor synthesis are also presented.

Original languageEnglish (US)
Title of host publicationIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Editors Anon
PublisherIEEE
Pages295-303
Number of pages9
StatePublished - 1996
EventProceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT'96 - Boston, MA, USA
Duration: Nov 6 1996Nov 8 1996

Other

OtherProceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT'96
CityBoston, MA, USA
Period11/6/9611/8/96

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Kim, K., Karri, R., & Potkonjak, M. (1996). Configurable spare processors: A new approach to system level fault-tolerance. In Anon (Ed.), IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (pp. 295-303). IEEE.