Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher

Kaijie Wu, Piyush Mishra, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate two systematic approaches to low-cost, low-latency CED for symmetric encryption algorithm RC6. The proposed techniques have been validated on FPGA implementations of RC6, one of the advanced encryption standard finalists.

Original languageEnglish (US)
Pages (from-to)31-39
Number of pages9
JournalMicroelectronics Journal
Volume34
Issue number1
DOIs
StatePublished - Jan 2003

Fingerprint

Error detection
Cryptography
redundancy
attack
hardware
Computer hardware
Redundancy
Field programmable gate arrays (FPGA)
Costs

Keywords

  • Concurrent error detection
  • Cryptanalysis
  • FPGA
  • RC6 block cipher

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. / Wu, Kaijie; Mishra, Piyush; Karri, Ramesh.

In: Microelectronics Journal, Vol. 34, No. 1, 01.2003, p. 31-39.

Research output: Contribution to journalArticle

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