Concurrent error detection architectures for symmetric block ciphers

Ramesh Karri, K Wu, Y. Kim,, Piyush Mishra

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original languageEnglish (US)
Title of host publicationProceedings of NASA Workshop on Military Applications of Programmable Designs and Technologies. Sept 2000. Greenbelt, MD
Pages1509-1517
StatePublished - 2000

Cite this

Karri, R., Wu, K., Kim, Y., & Mishra, P. (2000). Concurrent error detection architectures for symmetric block ciphers. In Proceedings of NASA Workshop on Military Applications of Programmable Designs and Technologies. Sept 2000. Greenbelt, MD (pp. 1509-1517)

Concurrent error detection architectures for symmetric block ciphers. / Karri, Ramesh; Wu, K; Kim, Y.; Mishra, Piyush.

Proceedings of NASA Workshop on Military Applications of Programmable Designs and Technologies. Sept 2000. Greenbelt, MD. 2000. p. 1509-1517.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Karri, R, Wu, K, Kim, Y & Mishra, P 2000, Concurrent error detection architectures for symmetric block ciphers. in Proceedings of NASA Workshop on Military Applications of Programmable Designs and Technologies. Sept 2000. Greenbelt, MD. pp. 1509-1517.
Karri R, Wu K, Kim, Y, Mishra P. Concurrent error detection architectures for symmetric block ciphers. In Proceedings of NASA Workshop on Military Applications of Programmable Designs and Technologies. Sept 2000. Greenbelt, MD. 2000. p. 1509-1517
Karri, Ramesh ; Wu, K ; Kim, Y. ; Mishra, Piyush. / Concurrent error detection architectures for symmetric block ciphers. Proceedings of NASA Workshop on Military Applications of Programmable Designs and Technologies. Sept 2000. Greenbelt, MD. 2000. pp. 1509-1517
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year = "2000",
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M3 - Conference contribution

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BT - Proceedings of NASA Workshop on Military Applications of Programmable Designs and Technologies. Sept 2000. Greenbelt, MD

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