Computer-aided design of fault-tolerant VLSI systems

Ramesh Karri, Karin Hogstedt, Alex Orailoglu

Research output: Contribution to journalArticle

Abstract

The authors present a flexible methodology for compiling an algorithmic description into an equivalent fault-tolerant VLSI circuit and a CAD framework embodying this methodology. Experimental designs illustrate and validate algorithms for automated synthesis of ICs featuring either self-recovery capability or enhanced reliability.

Original languageEnglish (US)
Pages (from-to)88-96
Number of pages9
JournalIEEE Design and Test of Computers
Volume13
Issue number3
DOIs
StatePublished - Sep 1996

Fingerprint

VLSI circuits
Design of experiments
Computer aided design
Recovery

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Computer-aided design of fault-tolerant VLSI systems. / Karri, Ramesh; Hogstedt, Karin; Orailoglu, Alex.

In: IEEE Design and Test of Computers, Vol. 13, No. 3, 09.1996, p. 88-96.

Research output: Contribution to journalArticle

Karri, Ramesh ; Hogstedt, Karin ; Orailoglu, Alex. / Computer-aided design of fault-tolerant VLSI systems. In: IEEE Design and Test of Computers. 1996 ; Vol. 13, No. 3. pp. 88-96.
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