Computer aided design of fault-tolerant application specific programmable processors

Ramesh Karri, Kyosun Kim, Miodrag Potkonjak

Research output: Contribution to journalArticle

Abstract

Application Specific Programmable Processors (ASPP) provide efficient implementation for any of m specified functionalities. Due to their flexibility and convenient performance-cost trade-offs, ASPPs are being developed by DSP, video, multimedia, and embedded IC manufacturers. In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs. ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis. Graceful degradation is supported by implementing multiple schedules of the ASPP applications, each with a different throughput constraint. In this paper, we do not consider concurrent error detection. The first ASPP fault tolerance technique minimizes the hardware resources while guaranteeing that the ASPP remains operational in the presence of all k-unit faults. On the other hand, the second fault tolerance technique maximizes the ASPP fault tolerance subject to constraints on the hardware resources. These ASPP fault tolerance techniques impose several unique tasks, such as fault-tolerant scheduling, hardware allocation, and application-to-faulty-unit assignment. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.

Original languageEnglish (US)
Pages (from-to)1272-1284
Number of pages13
JournalIEEE Transactions on Computers
Volume49
Issue number11
DOIs
StatePublished - Nov 2000

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Computer-aided Design
Fault-tolerant
Computer aided design
Fault tolerance
Fault Tolerance
Hardware
Degradation
Assignment
Scheduling
Synthesis
Resources
Unit
Error Detection
Error detection
Efficient Implementation
Multimedia
Costs
Concurrent
Schedule
Fault

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Computer aided design of fault-tolerant application specific programmable processors. / Karri, Ramesh; Kim, Kyosun; Potkonjak, Miodrag.

In: IEEE Transactions on Computers, Vol. 49, No. 11, 11.2000, p. 1272-1284.

Research output: Contribution to journalArticle

Karri, Ramesh ; Kim, Kyosun ; Potkonjak, Miodrag. / Computer aided design of fault-tolerant application specific programmable processors. In: IEEE Transactions on Computers. 2000 ; Vol. 49, No. 11. pp. 1272-1284.
@article{7600fd675cc042b980f9f0dfcfa76359,
title = "Computer aided design of fault-tolerant application specific programmable processors",
abstract = "Application Specific Programmable Processors (ASPP) provide efficient implementation for any of m specified functionalities. Due to their flexibility and convenient performance-cost trade-offs, ASPPs are being developed by DSP, video, multimedia, and embedded IC manufacturers. In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs. ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis. Graceful degradation is supported by implementing multiple schedules of the ASPP applications, each with a different throughput constraint. In this paper, we do not consider concurrent error detection. The first ASPP fault tolerance technique minimizes the hardware resources while guaranteeing that the ASPP remains operational in the presence of all k-unit faults. On the other hand, the second fault tolerance technique maximizes the ASPP fault tolerance subject to constraints on the hardware resources. These ASPP fault tolerance techniques impose several unique tasks, such as fault-tolerant scheduling, hardware allocation, and application-to-faulty-unit assignment. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.",
author = "Ramesh Karri and Kyosun Kim and Miodrag Potkonjak",
year = "2000",
month = "11",
doi = "10.1109/12.895942",
language = "English (US)",
volume = "49",
pages = "1272--1284",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "11",

}

TY - JOUR

T1 - Computer aided design of fault-tolerant application specific programmable processors

AU - Karri, Ramesh

AU - Kim, Kyosun

AU - Potkonjak, Miodrag

PY - 2000/11

Y1 - 2000/11

N2 - Application Specific Programmable Processors (ASPP) provide efficient implementation for any of m specified functionalities. Due to their flexibility and convenient performance-cost trade-offs, ASPPs are being developed by DSP, video, multimedia, and embedded IC manufacturers. In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs. ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis. Graceful degradation is supported by implementing multiple schedules of the ASPP applications, each with a different throughput constraint. In this paper, we do not consider concurrent error detection. The first ASPP fault tolerance technique minimizes the hardware resources while guaranteeing that the ASPP remains operational in the presence of all k-unit faults. On the other hand, the second fault tolerance technique maximizes the ASPP fault tolerance subject to constraints on the hardware resources. These ASPP fault tolerance techniques impose several unique tasks, such as fault-tolerant scheduling, hardware allocation, and application-to-faulty-unit assignment. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.

AB - Application Specific Programmable Processors (ASPP) provide efficient implementation for any of m specified functionalities. Due to their flexibility and convenient performance-cost trade-offs, ASPPs are being developed by DSP, video, multimedia, and embedded IC manufacturers. In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs. ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis. Graceful degradation is supported by implementing multiple schedules of the ASPP applications, each with a different throughput constraint. In this paper, we do not consider concurrent error detection. The first ASPP fault tolerance technique minimizes the hardware resources while guaranteeing that the ASPP remains operational in the presence of all k-unit faults. On the other hand, the second fault tolerance technique maximizes the ASPP fault tolerance subject to constraints on the hardware resources. These ASPP fault tolerance techniques impose several unique tasks, such as fault-tolerant scheduling, hardware allocation, and application-to-faulty-unit assignment. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.

UR - http://www.scopus.com/inward/record.url?scp=0034317340&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034317340&partnerID=8YFLogxK

U2 - 10.1109/12.895942

DO - 10.1109/12.895942

M3 - Article

AN - SCOPUS:0034317340

VL - 49

SP - 1272

EP - 1284

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 11

ER -