Compaction schemes with minimum test application time

Ozgur Sinanoglu, Alex Orailoglu

    Research output: Contribution to journalConference article

    Abstract

    Testing embedded cores in a System-On-a-Chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os. To relax the requirements on the test access mechanism at the core output side, we outline a space and time compaction scheme which minimizes test application time and required test bandwidth at the same time. We formulate the constraints on a mathematical basis for no aliasing compaction circuitry. The proposed compaction scheme is applicable to both combinational and sequential circuits. The experimental results illustrate that not only test application time is minimized but furthermore the associated area overhead is low as well.

    Original languageEnglish (US)
    Pages (from-to)199-204
    Number of pages6
    JournalProceedings of the Asian Test Symposium
    StatePublished - Dec 1 2001
    EventProceedings of the 10th Asian Test Symposium - Kyoto, Japan
    Duration: Nov 19 2001Nov 21 2001

    Fingerprint

    Compaction
    Sequential circuits
    Combinatorial circuits
    Bandwidth
    Testing

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Compaction schemes with minimum test application time. / Sinanoglu, Ozgur; Orailoglu, Alex.

    In: Proceedings of the Asian Test Symposium, 01.12.2001, p. 199-204.

    Research output: Contribution to journalConference article

    Sinanoglu, Ozgur ; Orailoglu, Alex. / Compaction schemes with minimum test application time. In: Proceedings of the Asian Test Symposium. 2001 ; pp. 199-204.
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