Compacting test responses for deeply embedded SoC cores

Ozgur Sinanoglu, Alex Orailoglu

    Research output: Contribution to journalArticle

    Abstract

    A fault-model-dependent compaction methodology that delivers the lowest possible test bandwidth with no aliasing of the modeled faults is proposed. This methodology is also computationally efficient because the aliasing analysis handles only a small subset of the faults. Subsequently, the proposed methodology is extended to scan-based cores.

    Original languageEnglish (US)
    Pages (from-to)22-30
    Number of pages9
    JournalIEEE Design and Test of Computers
    Volume20
    Issue number4
    DOIs
    StatePublished - Jul 1 2003

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    Compaction
    Bandwidth
    System-on-chip

    ASJC Scopus subject areas

    • Hardware and Architecture

    Cite this

    Compacting test responses for deeply embedded SoC cores. / Sinanoglu, Ozgur; Orailoglu, Alex.

    In: IEEE Design and Test of Computers, Vol. 20, No. 4, 01.07.2003, p. 22-30.

    Research output: Contribution to journalArticle

    Sinanoglu, Ozgur ; Orailoglu, Alex. / Compacting test responses for deeply embedded SoC cores. In: IEEE Design and Test of Computers. 2003 ; Vol. 20, No. 4. pp. 22-30.
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