Compact hardware architectures for BLAKE and LAKE hash functions

Jianzhou Li, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

BLAKE, one of SHA-3 candidates, and LAKE hash functions show the characteristic that the block length of the internal state is double its initial and final states, which means more registers are required for the implementation of the hash functions. In this paper, we explore shift register based compact hardware architectures for the two hash functions. This includes the 32-, 64-, and 128-bit datapath architectures for BLAKE. We provide post Place&Route performance results on both ASIC and FPGA platforms. The power consumption for each design is also given. Our results show that BLAKE has comparable performance when compared with the previous standard hash function of Whirlpool and less performance advantages over SHA-256. The results also indicate that BLAKE outperforms LAKE in the hardware implementation.

Original languageEnglish (US)
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
Pages2107-2110
Number of pages4
DOIs
StatePublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: May 30 2010Jun 2 2010

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period5/30/106/2/10

Fingerprint

Hash functions
Hardware
Shift registers
Application specific integrated circuits
Computer hardware
Field programmable gate arrays (FPGA)
Electric power utilization

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Li, J., & Karri, R. (2010). Compact hardware architectures for BLAKE and LAKE hash functions. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 2107-2110). [5537063] https://doi.org/10.1109/ISCAS.2010.5537063

Compact hardware architectures for BLAKE and LAKE hash functions. / Li, Jianzhou; Karri, Ramesh.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 2107-2110 5537063.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, J & Karri, R 2010, Compact hardware architectures for BLAKE and LAKE hash functions. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537063, pp. 2107-2110, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 5/30/10. https://doi.org/10.1109/ISCAS.2010.5537063
Li J, Karri R. Compact hardware architectures for BLAKE and LAKE hash functions. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 2107-2110. 5537063 https://doi.org/10.1109/ISCAS.2010.5537063
Li, Jianzhou ; Karri, Ramesh. / Compact hardware architectures for BLAKE and LAKE hash functions. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 2107-2110
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