Compact grid layouts of multi-level networks

S. Muthukrishnan, Mike Paterson, Suleyman Cenk Sahinalp, Torsten Suel

    Research output: Chapter in Book/Report/Conference proceedingChapter

    Abstract

    We consider the problem of generating layouts of multi-level networks, in particular, switching, sorting, and interconnection networks, as compactly as possible on VLSI grids. Besides traditional interest in these problems motivated by interconnection topologies in parallel computing and switching circuits in telecommunications, there is renewed interest in such layouts in the context of ATM (Asynchronous Transfer Mode) switches. Our results improve on the existing area bounds for these networks by factors of up to three.

    Original languageEnglish (US)
    Title of host publicationConference Proceedings of the Annual ACM Symposium on Theory of Computing
    PublisherACM
    Pages455-463
    Number of pages9
    StatePublished - 1999
    EventProceedings of the 1999 31st Annual ACM Symposium on Theory of Computing - FCRC '99 - Atlanta, GA, USA
    Duration: May 1 1999May 4 1999

    Other

    OtherProceedings of the 1999 31st Annual ACM Symposium on Theory of Computing - FCRC '99
    CityAtlanta, GA, USA
    Period5/1/995/4/99

    Fingerprint

    Switching circuits
    Asynchronous transfer mode
    Parallel processing systems
    Sorting
    Telecommunication
    Switches
    Topology

    ASJC Scopus subject areas

    • Software

    Cite this

    Muthukrishnan, S., Paterson, M., Sahinalp, S. C., & Suel, T. (1999). Compact grid layouts of multi-level networks. In Conference Proceedings of the Annual ACM Symposium on Theory of Computing (pp. 455-463). ACM.

    Compact grid layouts of multi-level networks. / Muthukrishnan, S.; Paterson, Mike; Sahinalp, Suleyman Cenk; Suel, Torsten.

    Conference Proceedings of the Annual ACM Symposium on Theory of Computing. ACM, 1999. p. 455-463.

    Research output: Chapter in Book/Report/Conference proceedingChapter

    Muthukrishnan, S, Paterson, M, Sahinalp, SC & Suel, T 1999, Compact grid layouts of multi-level networks. in Conference Proceedings of the Annual ACM Symposium on Theory of Computing. ACM, pp. 455-463, Proceedings of the 1999 31st Annual ACM Symposium on Theory of Computing - FCRC '99, Atlanta, GA, USA, 5/1/99.
    Muthukrishnan S, Paterson M, Sahinalp SC, Suel T. Compact grid layouts of multi-level networks. In Conference Proceedings of the Annual ACM Symposium on Theory of Computing. ACM. 1999. p. 455-463
    Muthukrishnan, S. ; Paterson, Mike ; Sahinalp, Suleyman Cenk ; Suel, Torsten. / Compact grid layouts of multi-level networks. Conference Proceedings of the Annual ACM Symposium on Theory of Computing. ACM, 1999. pp. 455-463
    @inbook{e4409651bde0415ba88161c7de2e850b,
    title = "Compact grid layouts of multi-level networks",
    abstract = "We consider the problem of generating layouts of multi-level networks, in particular, switching, sorting, and interconnection networks, as compactly as possible on VLSI grids. Besides traditional interest in these problems motivated by interconnection topologies in parallel computing and switching circuits in telecommunications, there is renewed interest in such layouts in the context of ATM (Asynchronous Transfer Mode) switches. Our results improve on the existing area bounds for these networks by factors of up to three.",
    author = "S. Muthukrishnan and Mike Paterson and Sahinalp, {Suleyman Cenk} and Torsten Suel",
    year = "1999",
    language = "English (US)",
    pages = "455--463",
    booktitle = "Conference Proceedings of the Annual ACM Symposium on Theory of Computing",
    publisher = "ACM",

    }

    TY - CHAP

    T1 - Compact grid layouts of multi-level networks

    AU - Muthukrishnan, S.

    AU - Paterson, Mike

    AU - Sahinalp, Suleyman Cenk

    AU - Suel, Torsten

    PY - 1999

    Y1 - 1999

    N2 - We consider the problem of generating layouts of multi-level networks, in particular, switching, sorting, and interconnection networks, as compactly as possible on VLSI grids. Besides traditional interest in these problems motivated by interconnection topologies in parallel computing and switching circuits in telecommunications, there is renewed interest in such layouts in the context of ATM (Asynchronous Transfer Mode) switches. Our results improve on the existing area bounds for these networks by factors of up to three.

    AB - We consider the problem of generating layouts of multi-level networks, in particular, switching, sorting, and interconnection networks, as compactly as possible on VLSI grids. Besides traditional interest in these problems motivated by interconnection topologies in parallel computing and switching circuits in telecommunications, there is renewed interest in such layouts in the context of ATM (Asynchronous Transfer Mode) switches. Our results improve on the existing area bounds for these networks by factors of up to three.

    UR - http://www.scopus.com/inward/record.url?scp=0032631762&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0032631762&partnerID=8YFLogxK

    M3 - Chapter

    SP - 455

    EP - 463

    BT - Conference Proceedings of the Annual ACM Symposium on Theory of Computing

    PB - ACM

    ER -