Communication limits of on-chip graphene plasmonic interconnects

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we develop physics-based performance models of plasmonic single waveguide (SWG) and parallel-plate waveguide (PPWG) interconnects using multilayer graphene (MLG) stack. While the SWG supports transverse magnetic plasmon modes, in the PPWG geometry, quasi-transverse electromagnetic modes emerge as the eigen modes. Using complex dynamical conductivity of MLG obtained from the Kubo formalism, we quantify the impact of the number of layers, electrostatic screening length, and the electrochemical potential on the transport characteristics of plasmon modes up to the terahertz frequencies (< 2 THz). Analytical models of the frequency-dependent distortion and attenuation of a propagating THz Gaussian pulse through the plasmonic interconnect are derived. While PPWG interconnects offer near dispersionless transmission, they have higher signal attenuation compared to the SWG interconnects implying a higher energy-per-bit for PPWG interconnects. We show that the bitrate density of PPWG interconnects is (1-2) orders of magnitude higher than that of electrical interconnects for length scales up to 1 mm. However, the energy dissipation of plasmonic interconnects increases exponentially with interconnect length. As such, the optimal length scales for plasmonic interconnects are several tens to a few hundreds of micrometers. By establishing a clear link between the device- and material-level parameters with the system-level performance, we show that plasmonic interconnects outperform copper interconnects at near-short and semi-global length scales.

Original languageEnglish (US)
Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
PublisherIEEE Computer Society
Pages45-51
Number of pages7
ISBN (Electronic)9781509054046
DOIs
StatePublished - May 2 2017
Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
Duration: Mar 14 2017Mar 15 2017

Other

Other18th International Symposium on Quality Electronic Design, ISQED 2017
CountryUnited States
CitySanta Clara
Period3/14/173/15/17

Fingerprint

Graphene
Waveguides
Communication
Multilayers
Analytical models
Electrostatics
Energy dissipation
Screening
Physics
Copper
Geometry

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Rakheja, S. (2017). Communication limits of on-chip graphene plasmonic interconnects. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 (pp. 45-51). [7918291] IEEE Computer Society. https://doi.org/10.1109/ISQED.2017.7918291

Communication limits of on-chip graphene plasmonic interconnects. / Rakheja, Shaloo.

Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. p. 45-51 7918291.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S 2017, Communication limits of on-chip graphene plasmonic interconnects. in Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017., 7918291, IEEE Computer Society, pp. 45-51, 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, United States, 3/14/17. https://doi.org/10.1109/ISQED.2017.7918291
Rakheja S. Communication limits of on-chip graphene plasmonic interconnects. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society. 2017. p. 45-51. 7918291 https://doi.org/10.1109/ISQED.2017.7918291
Rakheja, Shaloo. / Communication limits of on-chip graphene plasmonic interconnects. Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. pp. 45-51
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