Communicating novel computational state variables

Post-CMOS logic

Shaloo Rakheja, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The semiconducting material silicon forms the heart of the current complimentary metal?oxide semiconductor (CMOS) technology. Over the last four decades, the productivity of silicon technology has increased by a factor of more than a billion [1]. This growth in silicon technology was made possible by a steady reduction in the feature size, which helps pack more functionality per cost in a microprocessor. Today, the silicon-based semiconductor industry is an approximately US$270 billion market [1]. This exponential growth of the semiconductor industry was first observed by Dr. Gordon Moore. In 1965, Moore observed that the computing power of a microprocessor doubled every 18?24 months, and this observation later became known as Moore?s law [2]. In essence, Moore?s law is an economic law that serves to guide long-term planning and to set targets for research and development in the semiconductor industry. However, quantum-mechanical laws dictate that there are fundamental challenges associated with scaling on-chip components to below 10 nm [3]. A revolutionary innovation in semiconductor technology would be needed to sustain Moore?s law for advanced technology nodes below 10 nm [1], [4]. We examine performance trends of on-chip devices and interconnects upon dimensional scaling. This is followed by a discussion on emerging technologies and the repercussions of interconnects for these novel technologies.

Original languageEnglish (US)
Title of host publicationIEEE Nanotechnology Magazine
Pages15-23
Number of pages9
Volume7
Edition1
DOIs
StatePublished - 2013

Fingerprint

Semiconductor materials
Silicon
Microprocessor chips
Industry
Innovation
Productivity
Planning
Economics
Metals
Costs
Oxide semiconductors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Mechanical Engineering

Cite this

Rakheja, S., & Naeemi, A. (2013). Communicating novel computational state variables: Post-CMOS logic. In IEEE Nanotechnology Magazine (1 ed., Vol. 7, pp. 15-23). [6450165] https://doi.org/10.1109/MNANO.2012.2237314

Communicating novel computational state variables : Post-CMOS logic. / Rakheja, Shaloo; Naeemi, Azad.

IEEE Nanotechnology Magazine. Vol. 7 1. ed. 2013. p. 15-23 6450165.

Research output: Chapter in Book/Report/Conference proceedingChapter

Rakheja, S & Naeemi, A 2013, Communicating novel computational state variables: Post-CMOS logic. in IEEE Nanotechnology Magazine. 1 edn, vol. 7, 6450165, pp. 15-23. https://doi.org/10.1109/MNANO.2012.2237314
Rakheja S, Naeemi A. Communicating novel computational state variables: Post-CMOS logic. In IEEE Nanotechnology Magazine. 1 ed. Vol. 7. 2013. p. 15-23. 6450165 https://doi.org/10.1109/MNANO.2012.2237314
Rakheja, Shaloo ; Naeemi, Azad. / Communicating novel computational state variables : Post-CMOS logic. IEEE Nanotechnology Magazine. Vol. 7 1. ed. 2013. pp. 15-23
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