CNoC: High-radix clos network-on-chip

Yu Hsiang Kao, Ming Yang, N. Sertac Artan, H. Jonathan Chao

Research output: Contribution to journalArticle

Abstract

Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue (VOQ) buffer structure and packet mode dual round-robin matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNoC; 2) the design of hierarchical round-robin arbiter for high-radix high-speed NoC routers; and 3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node three-stage CNoC under uniform traffic increases from 62% to 78% by replacing the baseline virtual channel routers with PDRRM VOQ routers. We also compared the delay, power, and area performance of the 64-node CNoC with other NoC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces. The simulation results show that in general CNoC improves the throughput, low-load delay, and energy efficiency over the compared NoC topologies.

Original languageEnglish (US)
Article number6071084
Pages (from-to)1897-1910
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume30
Issue number12
DOIs
StatePublished - Dec 1 2011

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Keywords

  • Chip multiprocessor
  • clos network
  • high-radix NoC
  • network-on-chip

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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