CNoC

High-radix clos network-on-chip

Yu Hsiang Kao, Ming Yang, N. Sertac Artan, H. Jonathan Chao

Research output: Contribution to journalArticle

Abstract

Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue (VOQ) buffer structure and packet mode dual round-robin matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNoC; 2) the design of hierarchical round-robin arbiter for high-radix high-speed NoC routers; and 3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node three-stage CNoC under uniform traffic increases from 62% to 78% by replacing the baseline virtual channel routers with PDRRM VOQ routers. We also compared the delay, power, and area performance of the 64-node CNoC with other NoC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces. The simulation results show that in general CNoC improves the throughput, low-load delay, and energy efficiency over the compared NoC topologies.

Original languageEnglish (US)
Article number6071084
Pages (from-to)1897-1910
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume30
Issue number12
DOIs
StatePublished - Dec 2011

Fingerprint

Routers
Throughput
Topology
Network-on-chip
HIgh speed networks
Network performance
Scheduling algorithms
Resource allocation
Energy efficiency
Electric power utilization
Wire
Planning
Processing

Keywords

  • Chip multiprocessor
  • clos network
  • high-radix NoC
  • network-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

CNoC : High-radix clos network-on-chip. / Kao, Yu Hsiang; Yang, Ming; Artan, N. Sertac; Chao, H. Jonathan.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 12, 6071084, 12.2011, p. 1897-1910.

Research output: Contribution to journalArticle

Kao, Yu Hsiang ; Yang, Ming ; Artan, N. Sertac ; Chao, H. Jonathan. / CNoC : High-radix clos network-on-chip. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2011 ; Vol. 30, No. 12. pp. 1897-1910.
@article{ae80659c99b642459a42031b5f8782a6,
title = "CNoC: High-radix clos network-on-chip",
abstract = "Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue (VOQ) buffer structure and packet mode dual round-robin matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNoC; 2) the design of hierarchical round-robin arbiter for high-radix high-speed NoC routers; and 3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node three-stage CNoC under uniform traffic increases from 62{\%} to 78{\%} by replacing the baseline virtual channel routers with PDRRM VOQ routers. We also compared the delay, power, and area performance of the 64-node CNoC with other NoC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces. The simulation results show that in general CNoC improves the throughput, low-load delay, and energy efficiency over the compared NoC topologies.",
keywords = "Chip multiprocessor, clos network, high-radix NoC, network-on-chip",
author = "Kao, {Yu Hsiang} and Ming Yang and Artan, {N. Sertac} and Chao, {H. Jonathan}",
year = "2011",
month = "12",
doi = "10.1109/TCAD.2011.2164538",
language = "English (US)",
volume = "30",
pages = "1897--1910",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

TY - JOUR

T1 - CNoC

T2 - High-radix clos network-on-chip

AU - Kao, Yu Hsiang

AU - Yang, Ming

AU - Artan, N. Sertac

AU - Chao, H. Jonathan

PY - 2011/12

Y1 - 2011/12

N2 - Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue (VOQ) buffer structure and packet mode dual round-robin matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNoC; 2) the design of hierarchical round-robin arbiter for high-radix high-speed NoC routers; and 3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node three-stage CNoC under uniform traffic increases from 62% to 78% by replacing the baseline virtual channel routers with PDRRM VOQ routers. We also compared the delay, power, and area performance of the 64-node CNoC with other NoC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces. The simulation results show that in general CNoC improves the throughput, low-load delay, and energy efficiency over the compared NoC topologies.

AB - Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue (VOQ) buffer structure and packet mode dual round-robin matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNoC; 2) the design of hierarchical round-robin arbiter for high-radix high-speed NoC routers; and 3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node three-stage CNoC under uniform traffic increases from 62% to 78% by replacing the baseline virtual channel routers with PDRRM VOQ routers. We also compared the delay, power, and area performance of the 64-node CNoC with other NoC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces. The simulation results show that in general CNoC improves the throughput, low-load delay, and energy efficiency over the compared NoC topologies.

KW - Chip multiprocessor

KW - clos network

KW - high-radix NoC

KW - network-on-chip

UR - http://www.scopus.com/inward/record.url?scp=82155192300&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=82155192300&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2011.2164538

DO - 10.1109/TCAD.2011.2164538

M3 - Article

VL - 30

SP - 1897

EP - 1910

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 12

M1 - 6071084

ER -