Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process

Yeonwoo Ku, Ilku Nam, Sohmyung Ha, Kwyro Lee, Seonghwan Cho

Research output: Contribution to journalArticle

Abstract

This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-μm CMOS process. V-NPN has an inherently low nicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-/μm deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of - 87.4 dBc/Hz, - 111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 μW from the 1.8-V supply.

Original languageEnglish (US)
Pages (from-to)1363-1369
Number of pages7
JournalIEEE Transactions on Microwave Theory and Techniques
Volume54
Issue number4
DOIs
StatePublished - Jan 1 2006

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voltage controlled oscillators
Variable frequency oscillators
Phase noise
CMOS
Transistors
transistors
figure of merit
low noise
profiles

Keywords

  • Close-in phase noise
  • Flicker noise
  • Vertical-NPN (V-NPN) transistor
  • Voltage-controlled oscillator (VCO)

ASJC Scopus subject areas

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process. / Ku, Yeonwoo; Nam, Ilku; Ha, Sohmyung; Lee, Kwyro; Cho, Seonghwan.

In: IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 4, 01.01.2006, p. 1363-1369.

Research output: Contribution to journalArticle

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AU - Cho, Seonghwan

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N2 - This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-μm CMOS process. V-NPN has an inherently low nicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-/μm deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of - 87.4 dBc/Hz, - 111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 μW from the 1.8-V supply.

AB - This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-μm CMOS process. V-NPN has an inherently low nicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-/μm deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of - 87.4 dBc/Hz, - 111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 μW from the 1.8-V supply.

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