Can flexible, domain specific programmable logic prevent IP theft?

Xiaotong Cui, Kaijie Wu, Siddharth Garg, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fab-less design houses are outsourcing fabrication to third-party foundries to reduce costs. However, this has security consequences including intellectual property (IP) theft and piracy. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft and piracy. However, many obfuscation techniques through redesign or split manufacturing are costly in terms of manufacturing. We propose a High Level Synthesis and Analysis (HLSA) approach that leverages embedded programmable logic (EPL) to hide sensitive parts of the IP from a rogue foundry or a rogue actor in a foundry. While EPL was originally proposed to make the SoC programmable, we show that it can help a designer to thwart IP theft. Careful insertion of EPL increases the resistance to reverse engineering while managing the power consumption, area overhead and performance penalty. Our proposed security-aware HLSA design flow enables designers to explore this trade-off.

Original languageEnglish (US)
Title of host publication2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages153-157
Number of pages5
ISBN (Electronic)9781509036233
DOIs
StatePublished - Oct 25 2016
Event29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016 - Storrs, United States
Duration: Sep 19 2016Sep 20 2016

Other

Other29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
CountryUnited States
CityStorrs
Period9/19/169/20/16

Fingerprint

Intellectual property
Foundries
Reverse engineering
Outsourcing
Electric power utilization
Fabrication
Recovery
Costs
High level synthesis

Keywords

  • embedded programmable logic
  • high level synthesis and analysis
  • IP theft
  • SoC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture

Cite this

Cui, X., Wu, K., Garg, S., & Karri, R. (2016). Can flexible, domain specific programmable logic prevent IP theft? In 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016 (pp. 153-157). [7684088] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2016.7684088

Can flexible, domain specific programmable logic prevent IP theft? / Cui, Xiaotong; Wu, Kaijie; Garg, Siddharth; Karri, Ramesh.

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 153-157 7684088.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cui, X, Wu, K, Garg, S & Karri, R 2016, Can flexible, domain specific programmable logic prevent IP theft? in 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016., 7684088, Institute of Electrical and Electronics Engineers Inc., pp. 153-157, 29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016, Storrs, United States, 9/19/16. https://doi.org/10.1109/DFT.2016.7684088
Cui X, Wu K, Garg S, Karri R. Can flexible, domain specific programmable logic prevent IP theft? In 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 153-157. 7684088 https://doi.org/10.1109/DFT.2016.7684088
Cui, Xiaotong ; Wu, Kaijie ; Garg, Siddharth ; Karri, Ramesh. / Can flexible, domain specific programmable logic prevent IP theft?. 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 153-157
@inproceedings{52d07d19d63c4ee29d1b9c50aa8a9991,
title = "Can flexible, domain specific programmable logic prevent IP theft?",
abstract = "Fab-less design houses are outsourcing fabrication to third-party foundries to reduce costs. However, this has security consequences including intellectual property (IP) theft and piracy. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft and piracy. However, many obfuscation techniques through redesign or split manufacturing are costly in terms of manufacturing. We propose a High Level Synthesis and Analysis (HLSA) approach that leverages embedded programmable logic (EPL) to hide sensitive parts of the IP from a rogue foundry or a rogue actor in a foundry. While EPL was originally proposed to make the SoC programmable, we show that it can help a designer to thwart IP theft. Careful insertion of EPL increases the resistance to reverse engineering while managing the power consumption, area overhead and performance penalty. Our proposed security-aware HLSA design flow enables designers to explore this trade-off.",
keywords = "embedded programmable logic, high level synthesis and analysis, IP theft, SoC",
author = "Xiaotong Cui and Kaijie Wu and Siddharth Garg and Ramesh Karri",
year = "2016",
month = "10",
day = "25",
doi = "10.1109/DFT.2016.7684088",
language = "English (US)",
pages = "153--157",
booktitle = "2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - Can flexible, domain specific programmable logic prevent IP theft?

AU - Cui, Xiaotong

AU - Wu, Kaijie

AU - Garg, Siddharth

AU - Karri, Ramesh

PY - 2016/10/25

Y1 - 2016/10/25

N2 - Fab-less design houses are outsourcing fabrication to third-party foundries to reduce costs. However, this has security consequences including intellectual property (IP) theft and piracy. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft and piracy. However, many obfuscation techniques through redesign or split manufacturing are costly in terms of manufacturing. We propose a High Level Synthesis and Analysis (HLSA) approach that leverages embedded programmable logic (EPL) to hide sensitive parts of the IP from a rogue foundry or a rogue actor in a foundry. While EPL was originally proposed to make the SoC programmable, we show that it can help a designer to thwart IP theft. Careful insertion of EPL increases the resistance to reverse engineering while managing the power consumption, area overhead and performance penalty. Our proposed security-aware HLSA design flow enables designers to explore this trade-off.

AB - Fab-less design houses are outsourcing fabrication to third-party foundries to reduce costs. However, this has security consequences including intellectual property (IP) theft and piracy. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft and piracy. However, many obfuscation techniques through redesign or split manufacturing are costly in terms of manufacturing. We propose a High Level Synthesis and Analysis (HLSA) approach that leverages embedded programmable logic (EPL) to hide sensitive parts of the IP from a rogue foundry or a rogue actor in a foundry. While EPL was originally proposed to make the SoC programmable, we show that it can help a designer to thwart IP theft. Careful insertion of EPL increases the resistance to reverse engineering while managing the power consumption, area overhead and performance penalty. Our proposed security-aware HLSA design flow enables designers to explore this trade-off.

KW - embedded programmable logic

KW - high level synthesis and analysis

KW - IP theft

KW - SoC

UR - http://www.scopus.com/inward/record.url?scp=84999231125&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84999231125&partnerID=8YFLogxK

U2 - 10.1109/DFT.2016.7684088

DO - 10.1109/DFT.2016.7684088

M3 - Conference contribution

AN - SCOPUS:84999231125

SP - 153

EP - 157

BT - 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -