Behavior analysis of CMOS D flip-flops

H. Jonathan Chao, Cesar A. Johnston

Research output: Contribution to journalArticle

Abstract

The two D flip-flops generally considered to be the fastest (and most widely used) are analyzed. Their speed performance and their robustness are compared against clock skew when a two-phase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

Original languageEnglish (US)
Pages (from-to)1454-1458
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume24
Issue number5
DOIs
StatePublished - Oct 1989

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Flip flop circuits
Clocks
SPICE

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Behavior analysis of CMOS D flip-flops. / Chao, H. Jonathan; Johnston, Cesar A.

In: IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, 10.1989, p. 1454-1458.

Research output: Contribution to journalArticle

Chao, H. Jonathan ; Johnston, Cesar A. / Behavior analysis of CMOS D flip-flops. In: IEEE Journal of Solid-State Circuits. 1989 ; Vol. 24, No. 5. pp. 1454-1458.
@article{249c8c0cbba146708b1c603c1498e770,
title = "Behavior analysis of CMOS D flip-flops",
abstract = "The two D flip-flops generally considered to be the fastest (and most widely used) are analyzed. Their speed performance and their robustness are compared against clock skew when a two-phase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.",
author = "Chao, {H. Jonathan} and Johnston, {Cesar A.}",
year = "1989",
month = "10",
doi = "10.1109/JSSC.1989.572637",
language = "English (US)",
volume = "24",
pages = "1454--1458",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - Behavior analysis of CMOS D flip-flops

AU - Chao, H. Jonathan

AU - Johnston, Cesar A.

PY - 1989/10

Y1 - 1989/10

N2 - The two D flip-flops generally considered to be the fastest (and most widely used) are analyzed. Their speed performance and their robustness are compared against clock skew when a two-phase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

AB - The two D flip-flops generally considered to be the fastest (and most widely used) are analyzed. Their speed performance and their robustness are compared against clock skew when a two-phase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with SPICE simulation.

UR - http://www.scopus.com/inward/record.url?scp=0024749530&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024749530&partnerID=8YFLogxK

U2 - 10.1109/JSSC.1989.572637

DO - 10.1109/JSSC.1989.572637

M3 - Article

VL - 24

SP - 1454

EP - 1458

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -