AVF analysis acceleration via hierarchical fault pruning

Mihalis Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. In response, designers have introduced various methodologies that allow AVF calculation within reasonable time, at the cost of some loss of accuracy. In this paper, we present a method for calculating the AVF of design elements -using Statistical Fault Injection (SFI)- with equal accuracy but several orders of magnitude faster than traditional SFI techniques. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate the AVF numbers. The presented method has been applied on an Intel microprocessor, where experimental results corroborate its ability to achieve great speed-up while maintaining perfect accuracy in calculating AVF.

Original languageEnglish (US)
Title of host publicationProceedings - 16th IEEE European Test Symposium, ETS 2011
Pages87-92
Number of pages6
DOIs
StatePublished - Aug 29 2011
Event16th IEEE European Test Symposium, ETS 2011 - Trondheim, Norway
Duration: May 23 2011May 27 2011

Other

Other16th IEEE European Test Symposium, ETS 2011
CountryNorway
CityTrondheim
Period5/23/115/27/11

Fingerprint

Factor analysis
Microprocessor chips
Experiments

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Maniatakos, M., Tirumurti, C., Jas, A., & Makris, Y. (2011). AVF analysis acceleration via hierarchical fault pruning. In Proceedings - 16th IEEE European Test Symposium, ETS 2011 (pp. 87-92). [5957928] https://doi.org/10.1109/ETS.2011.42

AVF analysis acceleration via hierarchical fault pruning. / Maniatakos, Mihalis; Tirumurti, Chandra; Jas, Abhijit; Makris, Yiorgos.

Proceedings - 16th IEEE European Test Symposium, ETS 2011. 2011. p. 87-92 5957928.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maniatakos, M, Tirumurti, C, Jas, A & Makris, Y 2011, AVF analysis acceleration via hierarchical fault pruning. in Proceedings - 16th IEEE European Test Symposium, ETS 2011., 5957928, pp. 87-92, 16th IEEE European Test Symposium, ETS 2011, Trondheim, Norway, 5/23/11. https://doi.org/10.1109/ETS.2011.42
Maniatakos M, Tirumurti C, Jas A, Makris Y. AVF analysis acceleration via hierarchical fault pruning. In Proceedings - 16th IEEE European Test Symposium, ETS 2011. 2011. p. 87-92. 5957928 https://doi.org/10.1109/ETS.2011.42
Maniatakos, Mihalis ; Tirumurti, Chandra ; Jas, Abhijit ; Makris, Yiorgos. / AVF analysis acceleration via hierarchical fault pruning. Proceedings - 16th IEEE European Test Symposium, ETS 2011. 2011. pp. 87-92
@inproceedings{ca15e1d0a691450e8c24d4083b543414,
title = "AVF analysis acceleration via hierarchical fault pruning",
abstract = "The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. In response, designers have introduced various methodologies that allow AVF calculation within reasonable time, at the cost of some loss of accuracy. In this paper, we present a method for calculating the AVF of design elements -using Statistical Fault Injection (SFI)- with equal accuracy but several orders of magnitude faster than traditional SFI techniques. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate the AVF numbers. The presented method has been applied on an Intel microprocessor, where experimental results corroborate its ability to achieve great speed-up while maintaining perfect accuracy in calculating AVF.",
author = "Mihalis Maniatakos and Chandra Tirumurti and Abhijit Jas and Yiorgos Makris",
year = "2011",
month = "8",
day = "29",
doi = "10.1109/ETS.2011.42",
language = "English (US)",
isbn = "9780769544335",
pages = "87--92",
booktitle = "Proceedings - 16th IEEE European Test Symposium, ETS 2011",

}

TY - GEN

T1 - AVF analysis acceleration via hierarchical fault pruning

AU - Maniatakos, Mihalis

AU - Tirumurti, Chandra

AU - Jas, Abhijit

AU - Makris, Yiorgos

PY - 2011/8/29

Y1 - 2011/8/29

N2 - The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. In response, designers have introduced various methodologies that allow AVF calculation within reasonable time, at the cost of some loss of accuracy. In this paper, we present a method for calculating the AVF of design elements -using Statistical Fault Injection (SFI)- with equal accuracy but several orders of magnitude faster than traditional SFI techniques. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate the AVF numbers. The presented method has been applied on an Intel microprocessor, where experimental results corroborate its ability to achieve great speed-up while maintaining perfect accuracy in calculating AVF.

AB - The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. In response, designers have introduced various methodologies that allow AVF calculation within reasonable time, at the cost of some loss of accuracy. In this paper, we present a method for calculating the AVF of design elements -using Statistical Fault Injection (SFI)- with equal accuracy but several orders of magnitude faster than traditional SFI techniques. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate the AVF numbers. The presented method has been applied on an Intel microprocessor, where experimental results corroborate its ability to achieve great speed-up while maintaining perfect accuracy in calculating AVF.

UR - http://www.scopus.com/inward/record.url?scp=80052017953&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052017953&partnerID=8YFLogxK

U2 - 10.1109/ETS.2011.42

DO - 10.1109/ETS.2011.42

M3 - Conference contribution

AN - SCOPUS:80052017953

SN - 9780769544335

SP - 87

EP - 92

BT - Proceedings - 16th IEEE European Test Symposium, ETS 2011

ER -