Automatic verification of sequential circuits using temporal logic

Bhubaneswar Mishra, M Browne, EM Clarke, D Dill

Research output: Chapter in Book/Report/Conference proceedingChapter (peer-reviewed)

Original languageEnglish (US)
Title of host publicationIEEE tutorial on formal verification of hardware designs
EditorsM Yoeli
PublisherIEEE Computer Society Press
Pages166-175
StatePublished - 1991

Publication series

Namereprint

Cite this

Mishra, B., Browne, M., Clarke, EM., & Dill, D. (1991). Automatic verification of sequential circuits using temporal logic. In M. Yoeli (Ed.), IEEE tutorial on formal verification of hardware designs (pp. 166-175). (reprint). IEEE Computer Society Press.

Automatic verification of sequential circuits using temporal logic. / Mishra, Bhubaneswar; Browne, M; Clarke, EM; Dill, D.

IEEE tutorial on formal verification of hardware designs. ed. / M Yoeli. IEEE Computer Society Press, 1991. p. 166-175 (reprint).

Research output: Chapter in Book/Report/Conference proceedingChapter (peer-reviewed)

Mishra, B, Browne, M, Clarke, EM & Dill, D 1991, Automatic verification of sequential circuits using temporal logic. in M Yoeli (ed.), IEEE tutorial on formal verification of hardware designs. reprint, IEEE Computer Society Press, pp. 166-175.
Mishra B, Browne M, Clarke EM, Dill D. Automatic verification of sequential circuits using temporal logic. In Yoeli M, editor, IEEE tutorial on formal verification of hardware designs. IEEE Computer Society Press. 1991. p. 166-175. (reprint).
Mishra, Bhubaneswar ; Browne, M ; Clarke, EM ; Dill, D. / Automatic verification of sequential circuits using temporal logic. IEEE tutorial on formal verification of hardware designs. editor / M Yoeli. IEEE Computer Society Press, 1991. pp. 166-175 (reprint).
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