Architecture designs of a large-capacity Abacus ATM switch

H. Jonathan Chao, Jin Soo Park

Research output: Contribution to conferencePaper

Abstract

The Abacus switch we proposed has size limitation due to excessive routing delay in the switch fabric. Here, we suggest three different approaches to increase the capacity of the Abacus switch to, for instance, 1 Tb/s with existing CMOS technology. The first approach uses a memoryless multi-stage concentration network (MMCN), which reduces the routing delay and increases the capacity of the Abacus switch. The second approach uses a buffered multi-stage concentration network (BMCN), which uses a funnel concept and an input-buffered concentration modules (CMs) to relax the memory speed constraint. A new priority assignment scheme is proposed for the input-buffered CM to maintain the cell sequence of a virtual connection. The third approach allows the arbitration cycle exceeding a cell slot and thus resequences cells at the output ports. It is proved that the maximum degree of out-of-sequence is bounded in the worst case.

Original languageEnglish (US)
Pages369-374
Number of pages6
StatePublished - Dec 1 1998
EventProceedings of the IEEE GLOBECOM 1998 - The Bridge to the Global Integration - Sydney, NSW, Aust
Duration: Nov 8 1998Nov 12 1998

Other

OtherProceedings of the IEEE GLOBECOM 1998 - The Bridge to the Global Integration
CitySydney, NSW, Aust
Period11/8/9811/12/98

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Global and Planetary Change

Cite this

Chao, H. J., & Park, J. S. (1998). Architecture designs of a large-capacity Abacus ATM switch. 369-374. Paper presented at Proceedings of the IEEE GLOBECOM 1998 - The Bridge to the Global Integration, Sydney, NSW, Aust, .