An approach to energy-error tradeoffs in approximate ripple carry adders

Zvi Kedem, Vincent J. Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58X and by a median of 1.58X in 90nm transistor technology.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages211-216
Number of pages6
DOIs
StatePublished - 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
Duration: Aug 1 2011Aug 3 2011

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CountryJapan
CityFukuoka
Period8/1/118/3/11

Fingerprint

Adders
Transistors
Electric potential
Voltage scaling

Keywords

  • Approximate Adders
  • Geometric Programming
  • Low Energy Circuits
  • Voltage Scaling

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kedem, Z., Mooney, V. J., Muntimadugu, K. K., & Palem, K. V. (2011). An approach to energy-error tradeoffs in approximate ripple carry adders. In IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 (pp. 211-216). [5993638] https://doi.org/10.1109/ISLPED.2011.5993638

An approach to energy-error tradeoffs in approximate ripple carry adders. / Kedem, Zvi; Mooney, Vincent J.; Muntimadugu, Kirthi Krishna; Palem, Krishna V.

IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. p. 211-216 5993638.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kedem, Z, Mooney, VJ, Muntimadugu, KK & Palem, KV 2011, An approach to energy-error tradeoffs in approximate ripple carry adders. in IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011., 5993638, pp. 211-216, 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011, Fukuoka, Japan, 8/1/11. https://doi.org/10.1109/ISLPED.2011.5993638
Kedem Z, Mooney VJ, Muntimadugu KK, Palem KV. An approach to energy-error tradeoffs in approximate ripple carry adders. In IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. p. 211-216. 5993638 https://doi.org/10.1109/ISLPED.2011.5993638
Kedem, Zvi ; Mooney, Vincent J. ; Muntimadugu, Kirthi Krishna ; Palem, Krishna V. / An approach to energy-error tradeoffs in approximate ripple carry adders. IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. pp. 211-216
@inproceedings{755b10c27796499f84f624d563f3a43c,
title = "An approach to energy-error tradeoffs in approximate ripple carry adders",
abstract = "Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58X and by a median of 1.58X in 90nm transistor technology.",
keywords = "Approximate Adders, Geometric Programming, Low Energy Circuits, Voltage Scaling",
author = "Zvi Kedem and Mooney, {Vincent J.} and Muntimadugu, {Kirthi Krishna} and Palem, {Krishna V.}",
year = "2011",
doi = "10.1109/ISLPED.2011.5993638",
language = "English (US)",
isbn = "9781612846590",
pages = "211--216",
booktitle = "IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011",

}

TY - GEN

T1 - An approach to energy-error tradeoffs in approximate ripple carry adders

AU - Kedem, Zvi

AU - Mooney, Vincent J.

AU - Muntimadugu, Kirthi Krishna

AU - Palem, Krishna V.

PY - 2011

Y1 - 2011

N2 - Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58X and by a median of 1.58X in 90nm transistor technology.

AB - Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58X and by a median of 1.58X in 90nm transistor technology.

KW - Approximate Adders

KW - Geometric Programming

KW - Low Energy Circuits

KW - Voltage Scaling

UR - http://www.scopus.com/inward/record.url?scp=80052754056&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052754056&partnerID=8YFLogxK

U2 - 10.1109/ISLPED.2011.5993638

DO - 10.1109/ISLPED.2011.5993638

M3 - Conference contribution

AN - SCOPUS:80052754056

SN - 9781612846590

SP - 211

EP - 216

BT - IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011

ER -