An analog neural network processor and its application to high-speed character recognition

Bernhard E. Boser, Eduard Sackinger, Jane Bromley, Yann LeCun, Richard E. Howard, Lawrence D. Jackel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A high-speed programmable neural network chip and its application to character recognition are described. A network with over 130,000 connections has been implemented on a single chip and operates at a rate of over 1000 classifications per second. The chip performs up to 2000 multiplications and additions simultaneously. Its datapath is suitable for the convolutional architectures that are typical in pattern classification networks, but can also be configured for fully connected or feedback topologies. Computations were performed with 6 bits accuracy for the weights and 3 bits for the states. The chip uses analog processing internally for higher density and reduced power dissipation, but all input/output is digital to simplify system integration.

Original languageEnglish (US)
Title of host publicationProceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks
Editors Anon
PublisherPubl by IEEE
Pages415-420
Number of pages6
ISBN (Print)0780301641
StatePublished - 1991
EventInternational Joint Conference on Neural Networks - IJCNN-91-Seattle - Seattle, WA, USA
Duration: Jul 8 1991Jul 12 1991

Other

OtherInternational Joint Conference on Neural Networks - IJCNN-91-Seattle
CitySeattle, WA, USA
Period7/8/917/12/91

Fingerprint

Character recognition
Neural networks
Pattern recognition
Energy dissipation
Topology
Feedback
Processing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Boser, B. E., Sackinger, E., Bromley, J., LeCun, Y., Howard, R. E., & Jackel, L. D. (1991). An analog neural network processor and its application to high-speed character recognition. In Anon (Ed.), Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks (pp. 415-420). Publ by IEEE.

An analog neural network processor and its application to high-speed character recognition. / Boser, Bernhard E.; Sackinger, Eduard; Bromley, Jane; LeCun, Yann; Howard, Richard E.; Jackel, Lawrence D.

Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. ed. / Anon. Publ by IEEE, 1991. p. 415-420.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Boser, BE, Sackinger, E, Bromley, J, LeCun, Y, Howard, RE & Jackel, LD 1991, An analog neural network processor and its application to high-speed character recognition. in Anon (ed.), Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. Publ by IEEE, pp. 415-420, International Joint Conference on Neural Networks - IJCNN-91-Seattle, Seattle, WA, USA, 7/8/91.
Boser BE, Sackinger E, Bromley J, LeCun Y, Howard RE, Jackel LD. An analog neural network processor and its application to high-speed character recognition. In Anon, editor, Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. Publ by IEEE. 1991. p. 415-420
Boser, Bernhard E. ; Sackinger, Eduard ; Bromley, Jane ; LeCun, Yann ; Howard, Richard E. ; Jackel, Lawrence D. / An analog neural network processor and its application to high-speed character recognition. Proceedings. IJCNN-91-Seattle: International Joint Conference on Neural Networks. editor / Anon. Publ by IEEE, 1991. pp. 415-420
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