ALPS: An algorithm for pipeline data path synthesis

Ramesh Karri, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

While techniques for design of high performance computing systems have been well understood, software mechanisms for the automatic design of high performance application specific integrated circuits (ASICS) remain relatively u nexplored. Advances in levels of integration will make it feasible to support performance-enhancing structures on a single chip. With the increasing demand for high performance in real-time signal processing applications, the design of high speed ASICS merits immediate attention. In this paper, we develop software mechanisms for the high-level synthesis of high-performance VLSI systems. We have extended our interactive behavioral synthesis framework that provides scheduling with multiple constraints including performance and cost, to support scheduling for high-performance. The system is powerful enough to allow trade-offs along mnltiple dimensions. The software mechanisms to support highperformance include a pipeline scheduler, ALPS, that supports constraints including performance and cost. ALPS is a polynomial time algorithm. Experimental results have shown that (a) ALPS consistently synthesizes designs on the optimal-designs curve, (b) it can be used for rapid prototypiug as well as for detailed synthesis, and (c) the interplay between performance and cost results in a rich set of design alternatives.

Original languageEnglish (US)
Title of host publicationMICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture
PublisherIEEE Computer Society
Pages124-132
Number of pages9
VolumePart F129964
ISBN (Print)0897914600, 9780897914604
DOIs
StatePublished - Sep 1 1991
Event24th Annual International Symposium on Microarchitecture, MICRO 1991 - Albuquerque, United States
Duration: Nov 18 1991Nov 20 1991

Other

Other24th Annual International Symposium on Microarchitecture, MICRO 1991
CountryUnited States
CityAlbuquerque
Period11/18/9111/20/91

Fingerprint

Pipelines
Application specific integrated circuits
Scheduling
Costs
Signal processing
Polynomials

Keywords

  • Functional Pipelining
  • High-Level Synthesis

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Karri, R., & Orailoglu, A. (1991). ALPS: An algorithm for pipeline data path synthesis. In MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture (Vol. Part F129964, pp. 124-132). IEEE Computer Society. https://doi.org/10.1145/123465.123490

ALPS : An algorithm for pipeline data path synthesis. / Karri, Ramesh; Orailoglu, Alex.

MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture. Vol. Part F129964 IEEE Computer Society, 1991. p. 124-132.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Karri, R & Orailoglu, A 1991, ALPS: An algorithm for pipeline data path synthesis. in MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture. vol. Part F129964, IEEE Computer Society, pp. 124-132, 24th Annual International Symposium on Microarchitecture, MICRO 1991, Albuquerque, United States, 11/18/91. https://doi.org/10.1145/123465.123490
Karri R, Orailoglu A. ALPS: An algorithm for pipeline data path synthesis. In MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture. Vol. Part F129964. IEEE Computer Society. 1991. p. 124-132 https://doi.org/10.1145/123465.123490
Karri, Ramesh ; Orailoglu, Alex. / ALPS : An algorithm for pipeline data path synthesis. MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture. Vol. Part F129964 IEEE Computer Society, 1991. pp. 124-132
@inproceedings{cf6494f9f0a3423ba6973f324ba00731,
title = "ALPS: An algorithm for pipeline data path synthesis",
abstract = "While techniques for design of high performance computing systems have been well understood, software mechanisms for the automatic design of high performance application specific integrated circuits (ASICS) remain relatively u nexplored. Advances in levels of integration will make it feasible to support performance-enhancing structures on a single chip. With the increasing demand for high performance in real-time signal processing applications, the design of high speed ASICS merits immediate attention. In this paper, we develop software mechanisms for the high-level synthesis of high-performance VLSI systems. We have extended our interactive behavioral synthesis framework that provides scheduling with multiple constraints including performance and cost, to support scheduling for high-performance. The system is powerful enough to allow trade-offs along mnltiple dimensions. The software mechanisms to support highperformance include a pipeline scheduler, ALPS, that supports constraints including performance and cost. ALPS is a polynomial time algorithm. Experimental results have shown that (a) ALPS consistently synthesizes designs on the optimal-designs curve, (b) it can be used for rapid prototypiug as well as for detailed synthesis, and (c) the interplay between performance and cost results in a rich set of design alternatives.",
keywords = "Functional Pipelining, High-Level Synthesis",
author = "Ramesh Karri and Alex Orailoglu",
year = "1991",
month = "9",
day = "1",
doi = "10.1145/123465.123490",
language = "English (US)",
isbn = "0897914600",
volume = "Part F129964",
pages = "124--132",
booktitle = "MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - ALPS

T2 - An algorithm for pipeline data path synthesis

AU - Karri, Ramesh

AU - Orailoglu, Alex

PY - 1991/9/1

Y1 - 1991/9/1

N2 - While techniques for design of high performance computing systems have been well understood, software mechanisms for the automatic design of high performance application specific integrated circuits (ASICS) remain relatively u nexplored. Advances in levels of integration will make it feasible to support performance-enhancing structures on a single chip. With the increasing demand for high performance in real-time signal processing applications, the design of high speed ASICS merits immediate attention. In this paper, we develop software mechanisms for the high-level synthesis of high-performance VLSI systems. We have extended our interactive behavioral synthesis framework that provides scheduling with multiple constraints including performance and cost, to support scheduling for high-performance. The system is powerful enough to allow trade-offs along mnltiple dimensions. The software mechanisms to support highperformance include a pipeline scheduler, ALPS, that supports constraints including performance and cost. ALPS is a polynomial time algorithm. Experimental results have shown that (a) ALPS consistently synthesizes designs on the optimal-designs curve, (b) it can be used for rapid prototypiug as well as for detailed synthesis, and (c) the interplay between performance and cost results in a rich set of design alternatives.

AB - While techniques for design of high performance computing systems have been well understood, software mechanisms for the automatic design of high performance application specific integrated circuits (ASICS) remain relatively u nexplored. Advances in levels of integration will make it feasible to support performance-enhancing structures on a single chip. With the increasing demand for high performance in real-time signal processing applications, the design of high speed ASICS merits immediate attention. In this paper, we develop software mechanisms for the high-level synthesis of high-performance VLSI systems. We have extended our interactive behavioral synthesis framework that provides scheduling with multiple constraints including performance and cost, to support scheduling for high-performance. The system is powerful enough to allow trade-offs along mnltiple dimensions. The software mechanisms to support highperformance include a pipeline scheduler, ALPS, that supports constraints including performance and cost. ALPS is a polynomial time algorithm. Experimental results have shown that (a) ALPS consistently synthesizes designs on the optimal-designs curve, (b) it can be used for rapid prototypiug as well as for detailed synthesis, and (c) the interplay between performance and cost results in a rich set of design alternatives.

KW - Functional Pipelining

KW - High-Level Synthesis

UR - http://www.scopus.com/inward/record.url?scp=9444291751&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=9444291751&partnerID=8YFLogxK

U2 - 10.1145/123465.123490

DO - 10.1145/123465.123490

M3 - Conference contribution

AN - SCOPUS:9444291751

SN - 0897914600

SN - 9780897914604

VL - Part F129964

SP - 124

EP - 132

BT - MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture

PB - IEEE Computer Society

ER -