Algorithm level RE-computing with shifted operands - a register transfer level concurrent error detection technique

Kaijie Wu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Re-computing with Shifted Operands (RESO) is a logic level time redundancy based concurrent error detection (CED) technique. In RESO, logic level operations (and, nand, etc) are carried out twice - once on the basic input and once on the shifted input. Results from these two operations are compared to detect an error. Although using RESO operators in register transfer level (RTL) designs is straightforward, it entails time and area overhead. We developed an RT level CED technique called Algorithm level Re-computing with Shifted Operands (ARESO). ARESO does not use specialized RESO operators. Rather, it exploits RT level scheduling, pipelining, operator chaining, and multi-cycling to incorporate user specified error detection latencies. ARESO supports hardware vs. performance vs. error detection latency trade-offs. ARESO has been validated on practical design examples using Synopsys Behavior Compiler.

Original languageEnglish (US)
Title of host publicationIEEE International Test Conference (TC)
Number of pages8
StatePublished - 2000


ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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