Abstract
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the synopsys behavior complier (BC), to validate the schemes.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 864-875 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 10 |
| Issue number | 6 |
| DOIs | |
| State | Published - Dec 2002 |
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Keywords
- Concurrent error detection
- Fault-tolerance
- Reliability
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Algorithm level re-computing using implementation diversity : A register transfer level concurrent error detection technique. / Karri, Ramesh; Wu, Kaijie.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6, 12.2002, p. 864-875.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Algorithm level re-computing using implementation diversity
T2 - A register transfer level concurrent error detection technique
AU - Karri, Ramesh
AU - Wu, Kaijie
PY - 2002/12
Y1 - 2002/12
N2 - Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the synopsys behavior complier (BC), to validate the schemes.
AB - Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the synopsys behavior complier (BC), to validate the schemes.
KW - Concurrent error detection
KW - Fault-tolerance
KW - Reliability
UR - http://www.scopus.com/inward/record.url?scp=0037002343&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0037002343&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2002.808440
DO - 10.1109/TVLSI.2002.808440
M3 - Article
AN - SCOPUS:0037002343
VL - 10
SP - 864
EP - 875
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 6
ER -