Algorithm level re-computing using implementation diversity: A register transfer level concurrent error detection technique

Ramesh Karri, Kaijie Wu

Research output: Contribution to journalArticle

Abstract

Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the synopsys behavior complier (BC), to validate the schemes.

Original languageEnglish (US)
Pages (from-to)864-875
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume10
Issue number6
DOIs
StatePublished - Dec 2002

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Error detection
Redundancy
Fault detection

Keywords

  • Concurrent error detection
  • Fault-tolerance
  • Reliability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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