Adaptive reduction of the frequency search space for multi-vdd digital circuits

Chandra K.H. Suresh, Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges in terms of circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, in order to extract particular Vdd/fmax behavior of the die under test. This paper aims at adaptively reducing the search space for fmax at multiple levels by reusing the information previously obtained from the DUT during test-time. The proposed adaptive solution reduces the test/characterization time and costs at no area or test overhead.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
Pages292-295
Number of pages4
StatePublished - Oct 21 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: Mar 18 2013Mar 22 2013

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
CountryFrance
CityGrenoble
Period3/18/133/22/13

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suresh, C. K. H., Yilmaz, E., Ozev, S., & Sinanoglu, O. (2013). Adaptive reduction of the frequency search space for multi-vdd digital circuits. In Proceedings - Design, Automation and Test in Europe, DATE 2013 (pp. 292-295). [6513518] (Proceedings -Design, Automation and Test in Europe, DATE).