Activation of logic encrypted chips: Pre-test or post-test?

Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan J.V. Rajendran, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Logic encryption has been a popular defense against Intellectual Property (IP) piracy, hardware Trojans, reverse engineering, and IC overproduction. It protects a design from these threats by inserting key-gates that break the functionality when controlled by wrong keys. Researchers have taken multiple attempts in breaking logic encryption and leaking its secret key, while they also proposed difficult-to-break logic encryption techniques. Mainly, state-of-the-art logic encryption techniques pursue two different models that differ in when the manufactured chips are activated by loading the secret key on the chip's memory: activation prior to manufacturing test (pre-test) versus subsequent to manufacturing test (post-test). In this paper, we shed light on the interaction between manufacturing test and logic encryption. We assess and compare the pre-test and post-test activation models not only in terms of the impact of logic encryption on test parameters such as fault coverage, test pattern count and test power consumption, but also in terms of the impact of manufacturing test on the security of logic encryption. We outline a test data mining attack that can successfully determine the logic encryption key of a pre-test activated chip by utilizing the test data.

Original languageEnglish (US)
Title of host publicationProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages139-144
Number of pages6
ISBN (Electronic)9783981537062
StatePublished - Apr 25 2016
Event19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany
Duration: Mar 14 2016Mar 18 2016

Other

Other19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
CountryGermany
CityDresden
Period3/14/163/18/16

Fingerprint

Cryptography
Chemical activation
Reverse engineering
Intellectual property
Data mining
Electric power utilization
Hardware
Data storage equipment

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

Cite this

Yasin, M., Saeed, S. M., Rajendran, J. J. V., & Sinanoglu, O. (2016). Activation of logic encrypted chips: Pre-test or post-test? In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 (pp. 139-144). [7459294] Institute of Electrical and Electronics Engineers Inc..

Activation of logic encrypted chips : Pre-test or post-test? / Yasin, Muhammad; Saeed, Samah Mohamed; Rajendran, Jeyavijayan J.V.; Sinanoglu, Ozgur.

Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 139-144 7459294.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yasin, M, Saeed, SM, Rajendran, JJV & Sinanoglu, O 2016, Activation of logic encrypted chips: Pre-test or post-test? in Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016., 7459294, Institute of Electrical and Electronics Engineers Inc., pp. 139-144, 19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 3/14/16.
Yasin M, Saeed SM, Rajendran JJV, Sinanoglu O. Activation of logic encrypted chips: Pre-test or post-test? In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 139-144. 7459294
Yasin, Muhammad ; Saeed, Samah Mohamed ; Rajendran, Jeyavijayan J.V. ; Sinanoglu, Ozgur. / Activation of logic encrypted chips : Pre-test or post-test?. Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 139-144
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