A structured approach to post-silicon validation and debug using symbolic quick error detection

David Lin, Eshan Singh, Clark Barrett, Subhasish Mitra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing post-silicon validation and debug techniques are mostly ad hoc and often involve manual steps. Such ad hoc approaches cannot scale with increasing IC complexity. We present Symbolic Quick Error Detection (Symbolic QED), a structured approach to post-silicon validation and debug. Symbolic QED combines the following steps in a coordinated fashion: 1. Quick Error Detection (QED) tests that quickly detect bugs with short error detection latencies and high coverage. 2. Formal analysis techniques to localize bugs and generate minimal-length bug traces upon detection of the corresponding bugs. We demonstrate the practicality and effectiveness of Symbolic QED using the OpenSPARC T2, a 500-million-transistor open-source multicore System-on-Chip (SoC) design, and using "difficult" logic bug scenarios that occurred in various state-of-the-art commercial multicore SoCs. Our results show that Symbolic QED: (i) is fully automatic (unlike manual techniques in use today that can be extremely time-consuming and expensive); (ii) requires only a few hours in contrast to manual approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques; and, (iv) does not require any additional hardware.

Original languageEnglish (US)
Title of host publicationInternational Test Conference 2015, ITC 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467365789
DOIs
StatePublished - Nov 30 2015
Event46th IEEE International Test Conference, ITC 2015 - Anaheim, United States
Duration: Oct 6 2015Oct 8 2015

Publication series

NameProceedings - International Test Conference
Volume2015-November
ISSN (Print)1089-3539

Other

Other46th IEEE International Test Conference, ITC 2015
CountryUnited States
CityAnaheim
Period10/6/1510/8/15

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Keywords

  • Bounded Model Checking
  • Debug
  • Formal Debugging
  • Post-Silicon Validation and Debug
  • QED
  • Quick Error Detection
  • Symbolic Quick Error Detection

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Lin, D., Singh, E., Barrett, C., & Mitra, S. (2015). A structured approach to post-silicon validation and debug using symbolic quick error detection. In International Test Conference 2015, ITC 2015 - Proceedings [7342397] (Proceedings - International Test Conference; Vol. 2015-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2015.7342397