A statistical traffic model for on-chip interconnection networks

Vassos Soteriou Soteriou, Hangsheng Wang, Li Shiuan Peh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Network traffic modeling is a critical first step towards understanding and unraveling network power/performancerelated issues. Extensive prior research in the area of classic networks such as the Internet, Ethernet, and wireless LANs transporting TCP/IP, HTTP, and FTP traffic among others, has demonstrated how traffic models and model-based synthetic traffic generators can facilitate understanding of traffic characteristics and drive early-stage simulation to explore a large network design space. Though on-chip networks (a.k.a networks-on-chip (NoCs)) are becoming the de-facto scalable communication fabric in many-core systems-on-a-chip (SoCs) and chip multiprocessors (CMPs), no on-chip network traffic model that captures both spatial and temporal variations of traffic has been demonstrated yet. As available on-chip resources increase with technology scaling, enabling a myriad of new network architectures, NoCs need to be designed from the application's perspective. In this paper we propose such an empirically-derived network on-chip traffic model for homogeneous NoCs. Our comprehensive model is based on three statistical parameters described with a 3-tuple, and captures the spatio-temporal characteristics of NoC traffic accurately with less than 5% error when compared to actual NoC application traces gathered from fullsystem simulations of three different chip platforms. We illustrate two potential uses of our traffic model: how it allows us to characterize and gain insights on NoC traffic patterns, and how it can be used to generate synthetic traffic traces that can drive NoC design-space exploration.

Original languageEnglish (US)
Title of host publicationProceedings - 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006
Pages104-116
Number of pages13
StatePublished - Dec 1 2006
Event14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006 - Monterey, CA, United States
Duration: Sep 11 2006Sep 14 2006

Other

Other14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006
CountryUnited States
CityMonterey, CA
Period9/11/069/14/06

Fingerprint

Traffic Model
Interconnection Networks
Statistical Model
Chip
Traffic
Network Traffic
Trace
Traffic Modeling
Design Space Exploration
TCP/IP
Chip multiprocessors
Many-core
Network Modeling
Ethernet
Wireless LAN
HTTP
Network Architecture
Network Design
Network on chip
Network-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications
  • Software
  • Modeling and Simulation

Cite this

Soteriou, V. S., Wang, H., & Peh, L. S. (2006). A statistical traffic model for on-chip interconnection networks. In Proceedings - 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006 (pp. 104-116). [1698542]

A statistical traffic model for on-chip interconnection networks. / Soteriou, Vassos Soteriou; Wang, Hangsheng; Peh, Li Shiuan.

Proceedings - 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006. 2006. p. 104-116 1698542.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Soteriou, VS, Wang, H & Peh, LS 2006, A statistical traffic model for on-chip interconnection networks. in Proceedings - 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006., 1698542, pp. 104-116, 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006, Monterey, CA, United States, 9/11/06.
Soteriou VS, Wang H, Peh LS. A statistical traffic model for on-chip interconnection networks. In Proceedings - 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006. 2006. p. 104-116. 1698542
Soteriou, Vassos Soteriou ; Wang, Hangsheng ; Peh, Li Shiuan. / A statistical traffic model for on-chip interconnection networks. Proceedings - 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2006. 2006. pp. 104-116
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