A probabilistic spatial distribution model for wire faults in parallel network-on-chip links

Arseniy Vitkovskiy, Paul Christodoulides, Vassos Soteriou Soteriou

    Research output: Contribution to journalArticle

    Abstract

    High-performance chip multiprocessors contain numerous parallel-processing cores where a fabric devised as a network-on-chip (NoC) efficiently handles their escalating intertile communication demands. Unfortunately, prolonged operational stresses cause accelerated physically induced wearout leading to permanent metal wire faults in links. Where only a subset of wires may malfunction, enduring healthy wires are leveraged to sustain connectivity when a partially faulty link recovery mechanism is utilized, where its data recovery latency overhead is proportional to the number of consecutive faulty wires. With NoC link failure models being ultimately important, albeit being absent from existing literature, the construction of a mathematical model towards the understanding of the distribution of wire faults in parallel on-chip links is very critical. This paper steps in such a direction, where the objective is to find the probability of having a "fault segment" consisting of a certain number of consecutive "faulty" wires in a parallel NoC link. First, it is shown how the given problem can be reduced to an equivalent combinatorial problem through partitions and necklaces. Then the proposed algorithm counts certain classes of necklaces by making a separation between periodic and aperiodic cases. Finally, the resulting analytical model is tested successfully against a far more costly brute-force algorithm.

    Original languageEnglish (US)
    Article number410172
    JournalMathematical Problems in Engineering
    Volume2015
    DOIs
    StatePublished - Jan 1 2015

    Fingerprint

    Spatial Distribution
    Spatial distribution
    Necklace
    Fault
    Wire
    Consecutive
    Recovery
    Chip multiprocessors
    Combinatorial Problems
    Parallel Processing
    Analytical Model
    Latency
    Count
    Connectivity
    Chip
    High Performance
    Metals
    Directly proportional
    Partition
    Model

    ASJC Scopus subject areas

    • Mathematics(all)
    • Engineering(all)

    Cite this

    A probabilistic spatial distribution model for wire faults in parallel network-on-chip links. / Vitkovskiy, Arseniy; Christodoulides, Paul; Soteriou, Vassos Soteriou.

    In: Mathematical Problems in Engineering, Vol. 2015, 410172, 01.01.2015.

    Research output: Contribution to journalArticle

    Vitkovskiy, Arseniy ; Christodoulides, Paul ; Soteriou, Vassos Soteriou. / A probabilistic spatial distribution model for wire faults in parallel network-on-chip links. In: Mathematical Problems in Engineering. 2015 ; Vol. 2015.
    @article{fccc7d565da441fc8cbc335b5147316e,
    title = "A probabilistic spatial distribution model for wire faults in parallel network-on-chip links",
    abstract = "High-performance chip multiprocessors contain numerous parallel-processing cores where a fabric devised as a network-on-chip (NoC) efficiently handles their escalating intertile communication demands. Unfortunately, prolonged operational stresses cause accelerated physically induced wearout leading to permanent metal wire faults in links. Where only a subset of wires may malfunction, enduring healthy wires are leveraged to sustain connectivity when a partially faulty link recovery mechanism is utilized, where its data recovery latency overhead is proportional to the number of consecutive faulty wires. With NoC link failure models being ultimately important, albeit being absent from existing literature, the construction of a mathematical model towards the understanding of the distribution of wire faults in parallel on-chip links is very critical. This paper steps in such a direction, where the objective is to find the probability of having a {"}fault segment{"} consisting of a certain number of consecutive {"}faulty{"} wires in a parallel NoC link. First, it is shown how the given problem can be reduced to an equivalent combinatorial problem through partitions and necklaces. Then the proposed algorithm counts certain classes of necklaces by making a separation between periodic and aperiodic cases. Finally, the resulting analytical model is tested successfully against a far more costly brute-force algorithm.",
    author = "Arseniy Vitkovskiy and Paul Christodoulides and Soteriou, {Vassos Soteriou}",
    year = "2015",
    month = "1",
    day = "1",
    doi = "10.1155/2015/410172",
    language = "English (US)",
    volume = "2015",
    journal = "Mathematical Problems in Engineering",
    issn = "1024-123X",
    publisher = "Hindawi Publishing Corporation",

    }

    TY - JOUR

    T1 - A probabilistic spatial distribution model for wire faults in parallel network-on-chip links

    AU - Vitkovskiy, Arseniy

    AU - Christodoulides, Paul

    AU - Soteriou, Vassos Soteriou

    PY - 2015/1/1

    Y1 - 2015/1/1

    N2 - High-performance chip multiprocessors contain numerous parallel-processing cores where a fabric devised as a network-on-chip (NoC) efficiently handles their escalating intertile communication demands. Unfortunately, prolonged operational stresses cause accelerated physically induced wearout leading to permanent metal wire faults in links. Where only a subset of wires may malfunction, enduring healthy wires are leveraged to sustain connectivity when a partially faulty link recovery mechanism is utilized, where its data recovery latency overhead is proportional to the number of consecutive faulty wires. With NoC link failure models being ultimately important, albeit being absent from existing literature, the construction of a mathematical model towards the understanding of the distribution of wire faults in parallel on-chip links is very critical. This paper steps in such a direction, where the objective is to find the probability of having a "fault segment" consisting of a certain number of consecutive "faulty" wires in a parallel NoC link. First, it is shown how the given problem can be reduced to an equivalent combinatorial problem through partitions and necklaces. Then the proposed algorithm counts certain classes of necklaces by making a separation between periodic and aperiodic cases. Finally, the resulting analytical model is tested successfully against a far more costly brute-force algorithm.

    AB - High-performance chip multiprocessors contain numerous parallel-processing cores where a fabric devised as a network-on-chip (NoC) efficiently handles their escalating intertile communication demands. Unfortunately, prolonged operational stresses cause accelerated physically induced wearout leading to permanent metal wire faults in links. Where only a subset of wires may malfunction, enduring healthy wires are leveraged to sustain connectivity when a partially faulty link recovery mechanism is utilized, where its data recovery latency overhead is proportional to the number of consecutive faulty wires. With NoC link failure models being ultimately important, albeit being absent from existing literature, the construction of a mathematical model towards the understanding of the distribution of wire faults in parallel on-chip links is very critical. This paper steps in such a direction, where the objective is to find the probability of having a "fault segment" consisting of a certain number of consecutive "faulty" wires in a parallel NoC link. First, it is shown how the given problem can be reduced to an equivalent combinatorial problem through partitions and necklaces. Then the proposed algorithm counts certain classes of necklaces by making a separation between periodic and aperiodic cases. Finally, the resulting analytical model is tested successfully against a far more costly brute-force algorithm.

    UR - http://www.scopus.com/inward/record.url?scp=84927145326&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84927145326&partnerID=8YFLogxK

    U2 - 10.1155/2015/410172

    DO - 10.1155/2015/410172

    M3 - Article

    VL - 2015

    JO - Mathematical Problems in Engineering

    JF - Mathematical Problems in Engineering

    SN - 1024-123X

    M1 - 410172

    ER -