A dual-level matching algorithm for 3-stage Clos-network packet switches

H. Jonathan Chao, Soung Y. Liew, Zhigang Jing

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a new dual-level matching algorithm for 3-stage Clos-network packet switches, called d-MAC. Using a two-level matching algorithm, namely module-level matching and port-level matching, d-MAC is highly scalable and maintains high system performance. The module-level matching is responsible for finding the module-to-module matching according to the queue status of the switch, while the port-level matching is responsible for determining port-to-port matching and route assignment simultaneously. The two-level matchings are computed in a pipelined and parallel manner to speed up packet scheduling.

Original languageEnglish (US)
Title of host publicationProceedings - 11th Symposium on High Performance Interconnects, HOTI 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages38-43
Number of pages6
ISBN (Print)076952012X, 9780769520124
DOIs
StatePublished - 2003
Event11th Symposium on High Performance Interconnects, HOTI 2003 - Stanford, United States
Duration: Aug 20 2003Aug 22 2003

Other

Other11th Symposium on High Performance Interconnects, HOTI 2003
CountryUnited States
CityStanford
Period8/20/038/22/03

Fingerprint

Packet networks
Switches
Scheduling

Keywords

  • Chaos
  • Fabrics
  • Internet
  • Packet switching
  • Round robin
  • Routing
  • Scheduling algorithm
  • Switches
  • System performance
  • Traffic control

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Chao, H. J., Liew, S. Y., & Jing, Z. (2003). A dual-level matching algorithm for 3-stage Clos-network packet switches. In Proceedings - 11th Symposium on High Performance Interconnects, HOTI 2003 (pp. 38-43). [1231475] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CONECT.2003.1231475

A dual-level matching algorithm for 3-stage Clos-network packet switches. / Chao, H. Jonathan; Liew, Soung Y.; Jing, Zhigang.

Proceedings - 11th Symposium on High Performance Interconnects, HOTI 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 38-43 1231475.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chao, HJ, Liew, SY & Jing, Z 2003, A dual-level matching algorithm for 3-stage Clos-network packet switches. in Proceedings - 11th Symposium on High Performance Interconnects, HOTI 2003., 1231475, Institute of Electrical and Electronics Engineers Inc., pp. 38-43, 11th Symposium on High Performance Interconnects, HOTI 2003, Stanford, United States, 8/20/03. https://doi.org/10.1109/CONECT.2003.1231475
Chao HJ, Liew SY, Jing Z. A dual-level matching algorithm for 3-stage Clos-network packet switches. In Proceedings - 11th Symposium on High Performance Interconnects, HOTI 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 38-43. 1231475 https://doi.org/10.1109/CONECT.2003.1231475
Chao, H. Jonathan ; Liew, Soung Y. ; Jing, Zhigang. / A dual-level matching algorithm for 3-stage Clos-network packet switches. Proceedings - 11th Symposium on High Performance Interconnects, HOTI 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 38-43
@inproceedings{cba096056db34912a2243b4b5f0602c0,
title = "A dual-level matching algorithm for 3-stage Clos-network packet switches",
abstract = "In this paper, we present a new dual-level matching algorithm for 3-stage Clos-network packet switches, called d-MAC. Using a two-level matching algorithm, namely module-level matching and port-level matching, d-MAC is highly scalable and maintains high system performance. The module-level matching is responsible for finding the module-to-module matching according to the queue status of the switch, while the port-level matching is responsible for determining port-to-port matching and route assignment simultaneously. The two-level matchings are computed in a pipelined and parallel manner to speed up packet scheduling.",
keywords = "Chaos, Fabrics, Internet, Packet switching, Round robin, Routing, Scheduling algorithm, Switches, System performance, Traffic control",
author = "Chao, {H. Jonathan} and Liew, {Soung Y.} and Zhigang Jing",
year = "2003",
doi = "10.1109/CONECT.2003.1231475",
language = "English (US)",
isbn = "076952012X",
pages = "38--43",
booktitle = "Proceedings - 11th Symposium on High Performance Interconnects, HOTI 2003",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - A dual-level matching algorithm for 3-stage Clos-network packet switches

AU - Chao, H. Jonathan

AU - Liew, Soung Y.

AU - Jing, Zhigang

PY - 2003

Y1 - 2003

N2 - In this paper, we present a new dual-level matching algorithm for 3-stage Clos-network packet switches, called d-MAC. Using a two-level matching algorithm, namely module-level matching and port-level matching, d-MAC is highly scalable and maintains high system performance. The module-level matching is responsible for finding the module-to-module matching according to the queue status of the switch, while the port-level matching is responsible for determining port-to-port matching and route assignment simultaneously. The two-level matchings are computed in a pipelined and parallel manner to speed up packet scheduling.

AB - In this paper, we present a new dual-level matching algorithm for 3-stage Clos-network packet switches, called d-MAC. Using a two-level matching algorithm, namely module-level matching and port-level matching, d-MAC is highly scalable and maintains high system performance. The module-level matching is responsible for finding the module-to-module matching according to the queue status of the switch, while the port-level matching is responsible for determining port-to-port matching and route assignment simultaneously. The two-level matchings are computed in a pipelined and parallel manner to speed up packet scheduling.

KW - Chaos

KW - Fabrics

KW - Internet

KW - Packet switching

KW - Round robin

KW - Routing

KW - Scheduling algorithm

KW - Switches

KW - System performance

KW - Traffic control

UR - http://www.scopus.com/inward/record.url?scp=60649096310&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=60649096310&partnerID=8YFLogxK

U2 - 10.1109/CONECT.2003.1231475

DO - 10.1109/CONECT.2003.1231475

M3 - Conference contribution

AN - SCOPUS:60649096310

SN - 076952012X

SN - 9780769520124

SP - 38

EP - 43

BT - Proceedings - 11th Symposium on High Performance Interconnects, HOTI 2003

PB - Institute of Electrical and Electronics Engineers Inc.

ER -