A design methodology for the high-level synthesis of fault-tolerant ASICs

Alex Orailoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish (US)
Title of host publicationProceedings of IEEE Workshop on VLSI Signal Processing. October 1992. Napa Valley, CA
Pages417-426
StatePublished - 1992

Cite this

Orailoglu, A., & Karri, R. (1992). A design methodology for the high-level synthesis of fault-tolerant ASICs. In Proceedings of IEEE Workshop on VLSI Signal Processing. October 1992. Napa Valley, CA (pp. 417-426)

A design methodology for the high-level synthesis of fault-tolerant ASICs. / Orailoglu, Alex; Karri, Ramesh.

Proceedings of IEEE Workshop on VLSI Signal Processing. October 1992. Napa Valley, CA. 1992. p. 417-426.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Orailoglu, A & Karri, R 1992, A design methodology for the high-level synthesis of fault-tolerant ASICs. in Proceedings of IEEE Workshop on VLSI Signal Processing. October 1992. Napa Valley, CA. pp. 417-426.
Orailoglu A, Karri R. A design methodology for the high-level synthesis of fault-tolerant ASICs. In Proceedings of IEEE Workshop on VLSI Signal Processing. October 1992. Napa Valley, CA. 1992. p. 417-426
Orailoglu, Alex ; Karri, Ramesh. / A design methodology for the high-level synthesis of fault-tolerant ASICs. Proceedings of IEEE Workshop on VLSI Signal Processing. October 1992. Napa Valley, CA. 1992. pp. 417-426
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