A combinatorial application of necklaces: Modeling individual link failures in parallel network-on-Chip interconnect links

Arseniy Vitkovskiy, Paul Christodoulides, Vassos Soteriou Soteriou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The advent of the multicore era [1, 2] has made the execution of more complex software applications more efficient and faster. On-chip communication among the processing cores, in the form of packetized messages, is managed with the use of on-chip networks (NoCs) [3]. Routers handling on-chip communication are point-to-point topologically interconnected using parallel links laid onto the silicon surface comprising a number of individual parallel wires. With the underlying interconnect structure becoming denser, due to improvements in CMOS technology, parallel links become susceptible to wear-out [4], with permanent link failures inhibiting communication completely and indefinitely. It is hence critical to explore their failure patterns in the wires comprising these links and hence build mechanisms which can recover corrupted in-transit data [5, 6]; since no real data from chip manufacturers exist, the derivation of a mathematical model in aiding the understanding of the distribution of individual wire faults in parallel on-chip links becomes mandatory. This paper takes the first steps in such direction. First it is shown how the given problem reduces to an equivalent combinatorial problem through partitions and necklaces. Then a model that counts certain classes of necklaces is derived by making a separation between periodic and aperiodic cases. The model is tested against a brute-force algorithm to prove its exactness. Finally the obtained model is used in finding the probability distribution of the size of the fault segment of wires in a parallel NoC-based multicore chip.

Original languageEnglish (US)
Title of host publicationProceedings of the World Congress on Engineering 2012, WCE 2012
EditorsLen Gelman, Andrew Hunter, A. M. Korsunsky, S. I. Ao, David WL Hukins
PublisherNewswood Limited
Pages125-130
Number of pages6
Volume2197
ISBN (Print)9789881925138
StatePublished - Jan 1 2012
Event2012 World Congress on Engineering, WCE 2012 - London, United Kingdom
Duration: Jul 4 2012Jul 6 2012

Other

Other2012 World Congress on Engineering, WCE 2012
CountryUnited Kingdom
CityLondon
Period7/4/127/6/12

Fingerprint

Wire
Communication
Routers
Application programs
Probability distributions
Wear of materials
Mathematical models
Silicon
Network-on-chip
Processing

Keywords

  • Combinatorics
  • Fault-tolerance
  • Integer partition
  • Modeling
  • Necklace
  • Network-on-chip
  • Probability distribution

ASJC Scopus subject areas

  • Computer Science (miscellaneous)

Cite this

Vitkovskiy, A., Christodoulides, P., & Soteriou, V. S. (2012). A combinatorial application of necklaces: Modeling individual link failures in parallel network-on-Chip interconnect links. In L. Gelman, A. Hunter, A. M. Korsunsky, S. I. Ao, & D. WL. Hukins (Eds.), Proceedings of the World Congress on Engineering 2012, WCE 2012 (Vol. 2197, pp. 125-130). Newswood Limited.

A combinatorial application of necklaces : Modeling individual link failures in parallel network-on-Chip interconnect links. / Vitkovskiy, Arseniy; Christodoulides, Paul; Soteriou, Vassos Soteriou.

Proceedings of the World Congress on Engineering 2012, WCE 2012. ed. / Len Gelman; Andrew Hunter; A. M. Korsunsky; S. I. Ao; David WL Hukins. Vol. 2197 Newswood Limited, 2012. p. 125-130.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Vitkovskiy, A, Christodoulides, P & Soteriou, VS 2012, A combinatorial application of necklaces: Modeling individual link failures in parallel network-on-Chip interconnect links. in L Gelman, A Hunter, AM Korsunsky, SI Ao & DWL Hukins (eds), Proceedings of the World Congress on Engineering 2012, WCE 2012. vol. 2197, Newswood Limited, pp. 125-130, 2012 World Congress on Engineering, WCE 2012, London, United Kingdom, 7/4/12.
Vitkovskiy A, Christodoulides P, Soteriou VS. A combinatorial application of necklaces: Modeling individual link failures in parallel network-on-Chip interconnect links. In Gelman L, Hunter A, Korsunsky AM, Ao SI, Hukins DWL, editors, Proceedings of the World Congress on Engineering 2012, WCE 2012. Vol. 2197. Newswood Limited. 2012. p. 125-130
Vitkovskiy, Arseniy ; Christodoulides, Paul ; Soteriou, Vassos Soteriou. / A combinatorial application of necklaces : Modeling individual link failures in parallel network-on-Chip interconnect links. Proceedings of the World Congress on Engineering 2012, WCE 2012. editor / Len Gelman ; Andrew Hunter ; A. M. Korsunsky ; S. I. Ao ; David WL Hukins. Vol. 2197 Newswood Limited, 2012. pp. 125-130
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