A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW

Chul Kim, Siddharth Joshi, Chris Thomas, Sohmyung Ha, Abraham Akinin, Lawrence Larson, Gert Cauwenberghs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A CMOS integrated 4-channel capacitive harmonic rejection baseband receiver and 4x4 MIMO analog core spatial filter demonstrate >65dB harmonic folding rejection over 48MHz, and >48.5dB signal separation across 3MHz baseband. The 65nm CMOS IC occupies 3.27mm2 active area and consumes 0.67mW-1.28mW.

Original languageEnglish (US)
Title of host publication2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC304-C305
ISBN (Electronic)9784863485020
DOIs
StatePublished - Aug 31 2015
Event29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan
Duration: Jun 17 2015Jun 19 2015

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2015-August

Other

Other29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
CountryJapan
CityKyoto
Period6/17/156/19/15

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kim, C., Joshi, S., Thomas, C., Ha, S., Akinin, A., Larson, L., & Cauwenberghs, G. (2015). A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C304-C305). [7231300] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231300