A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS

Chul Kim, Sohmyung Ha, Chris Thomas, Siddharth Joshi, Jongkil Park, Lawrence Larson, Gert Cauwenberghs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a low-power high-linearity capacitive harmonic rejection mixer for cognitive radio applications. A passive mixer first receiver with capacitive 16-phase sinusoidal weighting implements harmonic rejection down-conversion, and an AC-coupled fully differential capacitor feedback transimpedance amplifier provides baseband linear voltage gain and band-pass filtering achieving an in-band IIP3 of +12.5 dBm at 320 MHz LO over 3 MHz baseband. The 1.62mm2 mixer in 65nm CMOS consumes 40 μW per I/Q complex output channel, and 7.82 mW for 16-phase PLL clock generation and distribution.

Original languageEnglish (US)
Title of host publicationESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
PublisherIEEE Computer Society
Pages227-230
Number of pages4
ISBN (Electronic)9781479956944
DOIs
StatePublished - Jan 1 2014
Event40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy
Duration: Sep 22 2014Sep 26 2014

Other

Other40th European Solid-State Circuit Conference, ESSCIRC 2014
CountryItaly
CityVenezia Lido
Period9/22/149/26/14

Fingerprint

Feedback amplifiers
Operational amplifiers
Phase locked loops
Cognitive radio
Clocks
Capacitors
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kim, C., Ha, S., Thomas, C., Joshi, S., Park, J., Larson, L., & Cauwenberghs, G. (2014). A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. In ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference (pp. 227-230). [6942063] IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2014.6942063

A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. / Kim, Chul; Ha, Sohmyung; Thomas, Chris; Joshi, Siddharth; Park, Jongkil; Larson, Lawrence; Cauwenberghs, Gert.

ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society, 2014. p. 227-230 6942063.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, C, Ha, S, Thomas, C, Joshi, S, Park, J, Larson, L & Cauwenberghs, G 2014, A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. in ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference., 6942063, IEEE Computer Society, pp. 227-230, 40th European Solid-State Circuit Conference, ESSCIRC 2014, Venezia Lido, Italy, 9/22/14. https://doi.org/10.1109/ESSCIRC.2014.6942063
Kim C, Ha S, Thomas C, Joshi S, Park J, Larson L et al. A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. In ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society. 2014. p. 227-230. 6942063 https://doi.org/10.1109/ESSCIRC.2014.6942063
Kim, Chul ; Ha, Sohmyung ; Thomas, Chris ; Joshi, Siddharth ; Park, Jongkil ; Larson, Lawrence ; Cauwenberghs, Gert. / A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society, 2014. pp. 227-230
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