3D NOC for many-core processors

Aamir Zia, Sachhidh Kannan, H. Jonathan Chao, Garrett S. Rose

Research output: Contribution to journalArticle

Abstract

With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15% less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.

Original languageEnglish (US)
Pages (from-to)1380-1390
Number of pages11
JournalMicroelectronics Journal
Volume42
Issue number12
DOIs
StatePublished - Dec 2011

Fingerprint

central processing units
chips
Topology
topology
Cytidine Monophosphate
Wire
communication
wire
Silicon
Oils and fats
fats
Telecommunication links
Scalability
Energy dissipation
Electric power utilization
Fats
mesh
Network-on-chip
emerging
dissipation

Keywords

  • 3D integration
  • Clos network
  • CMP
  • Low-power
  • Scalability
  • Through-silicon vias

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics

Cite this

3D NOC for many-core processors. / Zia, Aamir; Kannan, Sachhidh; Chao, H. Jonathan; Rose, Garrett S.

In: Microelectronics Journal, Vol. 42, No. 12, 12.2011, p. 1380-1390.

Research output: Contribution to journalArticle

Zia, A, Kannan, S, Chao, HJ & Rose, GS 2011, '3D NOC for many-core processors', Microelectronics Journal, vol. 42, no. 12, pp. 1380-1390. https://doi.org/10.1016/j.mejo.2011.09.013
Zia, Aamir ; Kannan, Sachhidh ; Chao, H. Jonathan ; Rose, Garrett S. / 3D NOC for many-core processors. In: Microelectronics Journal. 2011 ; Vol. 42, No. 12. pp. 1380-1390.
@article{e1828c1d777349b5b231491370f29a6d,
title = "3D NOC for many-core processors",
abstract = "With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15{\%} less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.",
keywords = "3D integration, Clos network, CMP, Low-power, Scalability, Through-silicon vias",
author = "Aamir Zia and Sachhidh Kannan and Chao, {H. Jonathan} and Rose, {Garrett S.}",
year = "2011",
month = "12",
doi = "10.1016/j.mejo.2011.09.013",
language = "English (US)",
volume = "42",
pages = "1380--1390",
journal = "Microelectronics Journal",
issn = "0959-8324",
publisher = "Elsevier BV",
number = "12",

}

TY - JOUR

T1 - 3D NOC for many-core processors

AU - Zia, Aamir

AU - Kannan, Sachhidh

AU - Chao, H. Jonathan

AU - Rose, Garrett S.

PY - 2011/12

Y1 - 2011/12

N2 - With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15% less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.

AB - With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15% less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.

KW - 3D integration

KW - Clos network

KW - CMP

KW - Low-power

KW - Scalability

KW - Through-silicon vias

UR - http://www.scopus.com/inward/record.url?scp=80955151744&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80955151744&partnerID=8YFLogxK

U2 - 10.1016/j.mejo.2011.09.013

DO - 10.1016/j.mejo.2011.09.013

M3 - Article

AN - SCOPUS:80955151744

VL - 42

SP - 1380

EP - 1390

JO - Microelectronics Journal

JF - Microelectronics Journal

SN - 0959-8324

IS - 12

ER -