A LSI framer chip, which provides a SONET-like time-division-multiplexed frame structure, and which has been implemented in a production 2- mu m CMOS technology, is described. Current samples of the chip have been tested functional to 160 Mb/s. The primary attributes presented include the circuit features used to achieve high-bit-rate operation, the level translation circuits which afford direct interfacing to ECL level clock and data signals, and the functional capabilities which lead to broad application of the chip in communications networks. Several examples of its use in a prototype broadband local access network are also described. The chip operates from a single 5-V supply, dissipates approximately 420 mW, and is packaged in a 68-pin leadless ceramic chip carrier (LCCC) package.
|Original language||English (US)|
|Journal||IEEE Journal of Solid-State Circuits|
|State||Published - Feb 1 1987|
ASJC Scopus subject areas
- Electrical and Electronic Engineering